| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetRegisterInfo.cpp | 61 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ in getMinimalPhysRegClass()
88 E = regclass_end(); I != E; ++I) in getAllocatableSet()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCRegisterInfo.h | 291 regclass_iterator regclass_end() const { return Classes+NumClasses; } in regclass_end() function
294 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 428 regclass_iterator regclass_end() const { return Classes+NumClasses; } in regclass_end() function
430 return make_range(regclass_begin(), regclass_end()); in regclasses()
434 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RenderMachineFunction.cpp | 249 rcEnd = tri->regclass_end(); in translateRegClassNamesToCurrentFunction()
352 rcEnd = tri->regclass_end(); in initWorst()
371 rcEnd = tri->regclass_end(); in initWorst()
434 rcEnd = tri->regclass_end(); in initCapacity()
480 rcEnd = tri->regclass_end(); in resetPressureAndLiveStates()
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| D | VirtRegMap.cpp | 83 E = TRI->regclass_end(); I != E; ++I) in runOnMachineFunction()
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| D | MachineLICM.cpp | 331 E = TRI->regclass_end(); I != E; ++I) in runOnMachineFunction()
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| D | RegAllocLinearScan.cpp | 408 E = tri_->regclass_end(); RCI != E; ++RCI) { in INITIALIZE_PASS_DEPENDENCY()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 678 regclass_iterator regclass_end() const { return RegClassEnd; } in regclass_end() function
680 return make_range(regclass_begin(), regclass_end()); in regclasses()
684 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 449 regclass_iterator regclass_end() const { return RegClassEnd; } in regclass_end() function
452 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 134 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ in getMinimalPhysRegClass()
165 E = regclass_end(); I != E; ++I) in getAllocatableSet()
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| D | RegisterClassInfo.cpp | 160 RI = TRI->regclass_begin(), RE = TRI->regclass_end(); RI != RE; ++RI) { in computePSetLimit()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 61 E = TRI->regclass_end(); in ResourcePriorityQueue()
368 E = TRI->regclass_end(); I != E; ++I) { in regPressureDelta()
375 E = TRI->regclass_end(); I != E; ++I) { in regPressureDelta()
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| D | ScheduleDAGRRList.cpp | 1663 E = TRI->regclass_end(); I != E; ++I) in RegReductionPQBase()
1931 E = TRI->regclass_end(); I != E; ++I) { in dumpRegPressure()
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| D | TargetLowering.cpp | 2358 E = RI->regclass_end(); RCI != E; ++RCI) { in getRegForInlineAsmConstraint()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 409 regclass_iterator regclass_end() const { return Classes+NumClasses; } in regclass_end() function
412 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 641 regclass_iterator regclass_end() const { return RegClassEnd; } in regclass_end() function
644 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBlockRanges.cpp | 233 for (auto I = TRI.regclass_begin(), E = TRI.regclass_end(); I != E; ++I) { in HexagonBlockRanges()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1551 E = TRI->regclass_end(); I != E; ++I) in RegReductionPQBase()
1821 E = TRI->regclass_end(); I != E; ++I) { in dumpRegPressure()
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| D | TargetLowering.cpp | 2758 E = RI->regclass_end(); RCI != E; ++RCI) { in getRegForInlineAsmConstraint()
|