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Searched refs:regclasses (Results 1 – 11 of 11) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp60 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue()
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta()
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta()
DScheduleDAGRRList.cpp1750 for (const TargetRegisterClass *RC : TRI->regclasses()) in RegReductionPQBase()
2056 for (const TargetRegisterClass *RC : TRI->regclasses()) { in dumpRegPressure()
DTargetLowering.cpp2995 for (const TargetRegisterClass *RC : RI->regclasses()) { in getRegForInlineAsmConstraint()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegUsageInfoCollector.cpp175 for (const TargetRegisterClass *RC : TRI.regclasses()) in computeCalleeSavedRegs()
DTargetRegisterInfo.cpp197 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
226 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
DRegisterClassInfo.cpp171 for (const TargetRegisterClass *C : TRI->regclasses()) { in computePSetLimit()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCRegisterInfo.h429 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DRDFRegisters.cpp34 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
DHexagonBlockRanges.cpp225 for (const TargetRegisterClass *RC : TRI.regclasses()) { in HexagonBlockRanges()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h679 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td582 // FIXME: This could be better modeled by looking at the regclasses of the operands.