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Searched refs:reglist (Results 1 – 22 of 22) sorted by relevance

/external/vixl/src/aarch32/
Dinstructions-aarch32.cc156 std::ostream& operator<<(std::ostream& os, SRegisterList reglist) { in operator <<() argument
157 SRegister first = reglist.GetFirstSRegister(); in operator <<()
158 SRegister last = reglist.GetLastSRegister(); in operator <<()
167 std::ostream& operator<<(std::ostream& os, DRegisterList reglist) { in operator <<() argument
168 DRegister first = reglist.GetFirstDRegister(); in operator <<()
169 DRegister last = reglist.GetLastDRegister(); in operator <<()
/external/v8/src/wasm/baseline/
Dliftoff-register.h317 inline std::ostream& operator<<(std::ostream& os, LiftoffRegList reglist) {
319 for (bool first = true; !reglist.is_empty(); first = false) {
320 LiftoffRegister reg = reglist.GetFirstRegSet();
321 reglist.clear(reg);
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb.td718 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
732 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
735 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
745 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
758 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
762 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
772 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1414 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1416 (tPOP pred:$p, reglist:$regs)>;
DARMInstrThumb2.td1529 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1544 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1559 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1574 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1598 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1616 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1634 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1652 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3111 reglist:$regs, variable_ops),
3113 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
[all …]
DARMInstrInfo.td368 def reglist : Operand<i32> {
2753 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2761 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2771 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2779 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2789 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2797 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2807 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2815 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2841 reglist:$regs, variable_ops),
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td768 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
783 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
786 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
796 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
809 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
813 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
823 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1531 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1533 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
DARMInstrThumb2.td1709 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1724 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1739 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1754 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1778 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1796 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1814 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1832 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3520 reglist:$regs, variable_ops),
3522 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
[all …]
DARMInstrInfo.td456 def reglist : Operand<i32> {
3131 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3140 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3151 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3160 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3171 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3180 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3191 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3200 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3230 reglist:$regs, variable_ops),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb.td785 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
800 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
803 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
813 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
826 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
830 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
840 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1674 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1676 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
DARMInstrThumb2.td1715 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1730 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1745 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1760 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1784 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1802 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1820 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1838 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3502 reglist:$regs, variable_ops),
3504 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
[all …]
DARMInstrInfo.td539 def reglist : Operand<i32> {
3241 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3250 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3261 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3270 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3281 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3290 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3301 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3310 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3340 reglist:$regs, variable_ops),
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DVirtRegRewriter.cpp123 SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist; in runOnMachineFunction() local
126 reglist.push_back(std::make_pair(&*I, I.getOperandNo())); in runOnMachineFunction()
127 for (unsigned N=0; N != reglist.size(); ++N) in runOnMachineFunction()
128 substitutePhysReg(reglist[N].first->getOperand(reglist[N].second), in runOnMachineFunction()
130 changed |= !reglist.empty(); in runOnMachineFunction()
/external/llvm/lib/Target/Mips/
DMicroMipsInstrInfo.td527 def reglist : Operand<i32> {
550 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
558 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
814 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
818 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMicroMipsInstrInfo.td534 def reglist : Operand<i32> {
557 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
565 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
908 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
912 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc8867 // (LDMIA_UPD SP, pred:$p, reglist:$regs)
9095 // (STMDB_UPD SP, pred:$p, reglist:$regs)
10649 // (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)
10658 // (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)
10667 // (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)
10676 // (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)
11269 // (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)
11278 // (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)
11287 // (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)
11696 // (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)
DARMDisassembler.c1917 unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
1994 if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1627 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
1699 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1869 unsigned reglist = fieldFromInstruction(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
1947 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1870 unsigned reglist = fieldFromInstruction(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
1948 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
/external/v8/
DBUILD.gn2341 "src/reglist.h",
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenInstrInfo.inc9607 reglist = 64,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenInstrInfo.inc11409 reglist = 151,