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Searched refs:regmask (Results 1 – 13 of 13) sorted by relevance

/external/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3.h1305 static inline void regmask_init(regmask_t *regmask) in regmask_init() argument
1307 memset(regmask, 0, sizeof(*regmask)); in regmask_init()
1310 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg) in regmask_set() argument
1316 (*regmask)[idx / 8] |= 1 << (idx % 8); in regmask_set()
1321 (*regmask)[idx / 8] |= 1 << (idx % 8); in regmask_set()
1353 static inline bool regmask_get(regmask_t *regmask, in regmask_get() argument
1360 if ((*regmask)[idx / 8] & (1 << (idx % 8))) in regmask_get()
1366 if ((*regmask)[idx / 8] & (1 << (idx % 8))) in regmask_get()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dipra-04.ll1 ; Test that the updated regmask on the call to @fun1 preserves %r14 and
4 ; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -enable-ipra -print-regmask-num-regs=-1 \
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/X86/
Ddbg-value-regmask-clobber.ll4 ; Values in registers should be clobbered by calls, which use a regmask instead
30 source_filename = "test/DebugInfo/X86/dbg-value-regmask-clobber.ll"
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dlivephysregs-regmask-clobber.mir4 # but both are clobbered by the regmask. Only V0 is re-defined before the
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Difcvt-regmask-noreturn.ll11 ; Prior to this change, the stack_chk call (which does not return) would clobber R0 in its regmask,
/external/llvm/test/CodeGen/ARM/
Difcvt-regmask-noreturn.ll11 ; Prior to this change, the stack_chk call (which does not return) would clobber R0 in its regmask,
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dregcoal-physreg.mir65 ; clobbered by the regmask on a call.
Daarch64-a57-fp-load-balancing.ll260 ; Test that regmask clobbering stops a chain sequence.
/external/llvm/test/DebugInfo/X86/
Ddbg-value-regmask-clobber.ll4 ; Values in registers should be clobbered by calls, which use a regmask instead
/external/v8/src/libsampler/
Dsampler.cc110 uint32_t regmask; member
/external/llvm/test/CodeGen/X86/
Dx86-shrink-wrapping.ll735 ; CHECK-LABEL: regmask:
772 define i32 @regmask(i32 %a, i32 %b, i32* %addr) {
777 ; Clobber a CSR so that we check something on the regmask
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dx86-shrink-wrapping.ll734 ; CHECK-LABEL: regmask:
771 define i32 @regmask(i32 %a, i32 %b, i32* %addr) {
776 ; Clobber a CSR so that we check something on the regmask
/external/llvm/test/CodeGen/AArch64/
Daarch64-a57-fp-load-balancing.ll260 ; Test that regmask clobbering stops a chain sequence.