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/external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/
DconversionInstructions.3.2.ll9 ; CHECK: %res1 = trunc i32 %src to i8
10 %res1 = trunc i32 %src to i8
17 ; CHECK: %res1 = zext i32 %src to i64
18 %res1 = zext i32 %src to i64
25 ; CHECK: %res1 = sext i32 %src to i64
26 %res1 = sext i32 %src to i64
33 ; CHECK: %res1 = fptrunc double %src to float
34 %res1 = fptrunc double %src to float
41 ; CHECK: %res1 = fpext float %src to double
42 %res1 = fpext float %src to double
[all …]
DbitwiseInstructions.3.2.ll10 ; CHECK: %res1 = shl i8 %x1, %x1
11 %res1 = shl i8 %x1, %x1
27 ; CHECK: %res1 = lshr i8 %x1, %x1
28 %res1 = lshr i8 %x1, %x1
38 ; CHECK: %res1 = ashr i8 %x1, %x1
39 %res1 = ashr i8 %x1, %x1
49 ; CHECK: %res1 = and i8 %x1, %x1
50 %res1 = and i8 %x1, %x1
57 ; CHECK: %res1 = or i8 %x1, %x1
58 %res1 = or i8 %x1, %x1
[all …]
DbinaryIntInstructions.3.2.ll10 ; CHECK: %res1 = add i1 %x1, %x1
11 %res1 = add i1 %x1, %x1
39 ; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1
40 %res1 = add nuw nsw <2 x i8> %x1, %x1
59 ; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1
60 %res1 = add nuw nsw <2 x i16> %x1, %x1
79 ; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1
80 %res1 = add nuw nsw <2 x i32> %x1, %x1
99 ; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1
100 %res1 = add nuw nsw <2 x i64> %x1, %x1
[all …]
DbinaryFloatInstructions.3.2.ll10 ; CHECK: %res1 = fadd float %x1, %x1
11 %res1 = fadd float %x1, %x1
33 ; CHECK: %res1 = fadd <2 x float> %x1, %x1
34 %res1 = fadd <2 x float> %x1, %x1
53 ; CHECK: %res1 = fadd <2 x double> %x1, %x1
54 %res1 = fadd <2 x double> %x1, %x1
73 ; CHECK: %res1 = fadd <2 x half> %x1, %x1
74 %res1 = fadd <2 x half> %x1, %x1
93 ; CHECK: %res1 = fsub float %x1, %x1
94 %res1 = fsub float %x1, %x1
[all …]
DvectorInstructions.3.2.ll10 ; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0
11 %res1 = extractelement <2 x i8> %x1, i32 0
18 ; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0
19 %res1 = insertelement <2 x i8> %x1, i8 0, i32 0
26 ; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
27 %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
/external/llvm/test/Bitcode/
DconversionInstructions.3.2.ll9 ; CHECK: %res1 = trunc i32 %src to i8
10 %res1 = trunc i32 %src to i8
17 ; CHECK: %res1 = zext i32 %src to i64
18 %res1 = zext i32 %src to i64
25 ; CHECK: %res1 = sext i32 %src to i64
26 %res1 = sext i32 %src to i64
33 ; CHECK: %res1 = fptrunc double %src to float
34 %res1 = fptrunc double %src to float
41 ; CHECK: %res1 = fpext float %src to double
42 %res1 = fpext float %src to double
[all …]
DbitwiseInstructions.3.2.ll10 ; CHECK: %res1 = shl i8 %x1, %x1
11 %res1 = shl i8 %x1, %x1
27 ; CHECK: %res1 = lshr i8 %x1, %x1
28 %res1 = lshr i8 %x1, %x1
38 ; CHECK: %res1 = ashr i8 %x1, %x1
39 %res1 = ashr i8 %x1, %x1
49 ; CHECK: %res1 = and i8 %x1, %x1
50 %res1 = and i8 %x1, %x1
57 ; CHECK: %res1 = or i8 %x1, %x1
58 %res1 = or i8 %x1, %x1
[all …]
DbinaryIntInstructions.3.2.ll10 ; CHECK: %res1 = add i1 %x1, %x1
11 %res1 = add i1 %x1, %x1
39 ; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1
40 %res1 = add nuw nsw <2 x i8> %x1, %x1
59 ; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1
60 %res1 = add nuw nsw <2 x i16> %x1, %x1
79 ; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1
80 %res1 = add nuw nsw <2 x i32> %x1, %x1
99 ; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1
100 %res1 = add nuw nsw <2 x i64> %x1, %x1
[all …]
DbinaryFloatInstructions.3.2.ll10 ; CHECK: %res1 = fadd float %x1, %x1
11 %res1 = fadd float %x1, %x1
33 ; CHECK: %res1 = fadd <2 x float> %x1, %x1
34 %res1 = fadd <2 x float> %x1, %x1
53 ; CHECK: %res1 = fadd <2 x double> %x1, %x1
54 %res1 = fadd <2 x double> %x1, %x1
73 ; CHECK: %res1 = fadd <2 x half> %x1, %x1
74 %res1 = fadd <2 x half> %x1, %x1
93 ; CHECK: %res1 = fsub float %x1, %x1
94 %res1 = fsub float %x1, %x1
[all …]
DvectorInstructions.3.2.ll10 ; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0
11 %res1 = extractelement <2 x i8> %x1, i32 0
18 ; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0
19 %res1 = insertelement <2 x i8> %x1, i8 0, i32 0
26 ; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
27 %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
/external/libaom/libaom/aom_dsp/x86/
Dfwd_txfm_sse2.h68 int res0, res1; in check_epi16_overflow_x8() local
70 res1 = check_epi16_overflow_x4(preg4, preg5, preg6, preg7); in check_epi16_overflow_x8()
71 return res0 + res1; in check_epi16_overflow_x8()
79 int res0, res1; in check_epi16_overflow_x12() local
81 res1 = check_epi16_overflow_x4(preg4, preg5, preg6, preg7); in check_epi16_overflow_x12()
83 return res0 + res1; in check_epi16_overflow_x12()
93 int res0, res1; in check_epi16_overflow_x16() local
95 res1 = check_epi16_overflow_x4(preg4, preg5, preg6, preg7); in check_epi16_overflow_x16()
98 if (!res1) res1 = check_epi16_overflow_x4(preg12, preg13, preg14, preg15); in check_epi16_overflow_x16()
100 return res0 + res1; in check_epi16_overflow_x16()
[all …]
/external/icu/icu4c/source/test/intltest/
Dtchcfmt.cpp51 UnicodeString res1, res2; in TestSimpleExample() local
62 res1 = form->format(i, str, fpos, status ); in TestSimpleExample()
69 … it_logln(UnicodeString("") + ix + UnicodeString(" -> ") + res1 + UnicodeString(" -> ") + res2); in TestSimpleExample()
174 UnicodeString res1, res2; in TestComplexExample() local
175 pattform->toPattern( res1 ); in TestComplexExample()
176 it_logln("MessageFormat toPattern: " + res1); in TestComplexExample()
177 fileform->toPattern( res1 ); in TestComplexExample()
178 it_logln("ChoiceFormat toPattern: " + res1); in TestComplexExample()
179 if (res1 == "-1#are corrupted files|0#are no files|1#is one file|2#are {2} files") { in TestComplexExample()
349 form_pat.toPattern( res1 ); in TestComplexExample()
[all …]
/external/libvpx/libvpx/vp8/common/mips/msa/
Didct_msa.c91 v4i32 res0, res1, res2, res3; in idct4x4_addblk_msa() local
104 ILVR_B4_SW(zero, pred0, zero, pred1, zero, pred2, zero, pred3, res0, res1, in idct4x4_addblk_msa()
106 ILVR_H4_SW(zero, res0, zero, res1, zero, res2, zero, res3, res0, res1, res2, in idct4x4_addblk_msa()
108 ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3); in idct4x4_addblk_msa()
110 res1 = CLIP_SW_0_255(res1); in idct4x4_addblk_msa()
113 PCKEV_B2_SW(res0, res1, res2, res3, vt0, vt1); in idct4x4_addblk_msa()
121 v8i16 vec, res0, res1, res2, res3, dst0, dst1; in idct4x4_addconst_msa() local
128 ILVR_B4_SH(zero, pred0, zero, pred1, zero, pred2, zero, pred3, res0, res1, in idct4x4_addconst_msa()
130 ADD4(res0, vec, res1, vec, res2, vec, res3, vec, res0, res1, res2, res3); in idct4x4_addconst_msa()
131 CLIP_SH4_0_255(res0, res1, res2, res3); in idct4x4_addconst_msa()
[all …]
/external/ltp/testcases/kernel/syscalls/getcwd/
Dgetcwd03.c47 char *res1 = NULL; in verify_getcwd() local
52 res1 = getcwd(NULL, 0); in verify_getcwd()
53 if (!res1) { in verify_getcwd()
69 if (strcmp(res1, res2)) { in verify_getcwd()
72 res1, res2); in verify_getcwd()
79 if (strcmp(link, SAFE_BASENAME(res1))) { in verify_getcwd()
88 free(res1); in verify_getcwd()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dshuffle-of-splat-multiuses.ll13 %res1 = shufflevector<2 x double> %res, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
15 ret <2 x double> %res1
25 …%res1 = shufflevector<4 x double> %res, <4 x double> undef, <4 x i32> <i32 2, i32 0, i32 undef, i3…
27 ret <4 x double> %res1
45 …%res1 = shufflevector<8 x float> %res, <8 x float> undef, <8 x i32> <i32 2, i32 0, i32 undef, i32 …
47 ret <8 x float> %res1
56 …%res1 = shufflevector <4 x i32> %res, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 und…
57 ret <4 x i32> %res1
66 …%res1 = shufflevector <4 x i32> %res, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 und…
67 ret <4 x i32> %res1
[all …]
/external/llvm/test/CodeGen/X86/
Davx512bwvl-intrinsics-fast-isel.ll19 %res1 = bitcast <16 x i8> %res0 to <2 x i64>
20 ret <2 x i64> %res1
40 %res1 = select <16 x i1> %arg1, <16 x i8> %res0, <16 x i8> %arg0
41 %res2 = bitcast <16 x i8> %res1 to <2 x i64>
61 %res1 = select <16 x i1> %arg0, <16 x i8> %res0, <16 x i8> zeroinitializer
62 %res2 = bitcast <16 x i8> %res1 to <2 x i64>
78 %res1 = bitcast <32 x i8> %res0 to <4 x i64>
79 ret <4 x i64> %res1
99 %res1 = select <32 x i1> %arg1, <32 x i8> %res0, <32 x i8> %arg0
100 %res2 = bitcast <32 x i8> %res1 to <4 x i64>
[all …]
Davx512dq-intrinsics.ll15 …%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2qq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1, …
16 %res2 = add <8 x i64> %res, %res1
31 …%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1,…
32 %res2 = add <8 x i64> %res, %res1
47 …%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtps2qq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, i…
48 %res2 = add <8 x i64> %res, %res1
63 …%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtps2uqq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, …
64 %res2 = add <8 x i64> %res, %res1
79 …%res1 = call <8 x double> @llvm.x86.avx512.mask.cvtqq2pd.512(<8 x i64> %x0, <8 x double> %x1, i8 -…
80 %res2 = fadd <8 x double> %res, %res1
[all …]
Davx512-intrinsics-fast-isel.ll19 %res1 = bitcast <16 x i32> %res0 to <8 x i64>
20 ret <8 x i64> %res1
40 %res1 = select <16 x i1> %arg1, <16 x i32> %res0, <16 x i32> %arg0
41 %res2 = bitcast <16 x i32> %res1 to <8 x i64>
61 %res1 = select <16 x i1> %arg0, <16 x i32> %res0, <16 x i32> zeroinitializer
62 %res2 = bitcast <16 x i32> %res1 to <8 x i64>
95 %res1 = select <8 x i1> %arg1, <8 x i64> %res0, <8 x i64> %a0
96 ret <8 x i64> %res1
114 %res1 = select <8 x i1> %arg0, <8 x i64> %res0, <8 x i64> zeroinitializer
115 ret <8 x i64> %res1
[all …]
/external/libvpx/libvpx/vpx_dsp/x86/
Dfwd_txfm_sse2.h70 int res0, res1; in check_epi16_overflow_x8() local
72 res1 = check_epi16_overflow_x4(preg4, preg5, preg6, preg7); in check_epi16_overflow_x8()
73 return res0 + res1; in check_epi16_overflow_x8()
81 int res0, res1; in check_epi16_overflow_x12() local
83 res1 = check_epi16_overflow_x4(preg4, preg5, preg6, preg7); in check_epi16_overflow_x12()
85 return res0 + res1; in check_epi16_overflow_x12()
95 int res0, res1; in check_epi16_overflow_x16() local
97 res1 = check_epi16_overflow_x4(preg4, preg5, preg6, preg7); in check_epi16_overflow_x16()
100 if (!res1) res1 = check_epi16_overflow_x4(preg12, preg13, preg14, preg15); in check_epi16_overflow_x16()
102 return res0 + res1; in check_epi16_overflow_x16()
[all …]
/external/u-boot/arch/powerpc/include/asm/
Dimmap_8xx.h21 char res1[2]; member
52 char res1[0x20]; member
82 char res1[0x24]; member
101 char res1[0x14]; member
154 char res1[0x10]; member
182 char res1[3]; member
198 char res1[4]; member
232 char res1[8]; member
251 char res1[0xe]; member
281 char res1[2]; member
[all …]
Dimmap_83xx.h38 u8 res1[0x14]; member
84 u8 res1[2]; member
109 u8 res1[11]; member
183 u8 res1[0xDC]; member
198 u8 res1[0xDC]; member
244 u8 res1[0xE8]; member
273 u8 res1[0x38]; member
293 u8 res1[0x70]; member
349 u8 res1[3]; member
360 u32 res1[0x6]; /* 0x38-0x49 reserved */ member
[all …]
/external/llvm/test/Transforms/ConstantHoisting/ARM/
Dbad-cases.ll53 ; CHECK: %res1 = sdiv i32 %l1, 1000000000
59 %l1 = phi i32 [%res1, %loop], [%in1, %entry]
61 %res1 = sdiv i32 %l1, 1000000000
62 store volatile i32 %res1, i32* %addr
65 %again = icmp eq i32 %res1, %res2
74 ; CHECK: %res1 = udiv i32 %l1, 1000000000
81 %l1 = phi i32 [%res1, %loop], [%in1, %entry]
83 %res1 = udiv i32 %l1, 1000000000
84 store volatile i32 %res1, i32* %addr
87 %again = icmp eq i32 %res1, %res2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dasm-18.ll161 %res1 = extractvalue { i32, i32 } %res, 0
163 %trunc1 = trunc i32 %res1 to i8
184 %res1 = extractvalue { i32, i32 } %res, 0
186 %trunc1 = trunc i32 %res1 to i16
333 %res1 = call i32 asm "stepa $0", "=h"()
334 %and1 = and i32 %res1, 65535
352 %res1 = call i32 asm "stepa $0", "=r"()
353 %and1 = and i32 %res1, 65535
373 %res1 = call i32 asm "stepa $0", "=h"()
374 %or1 = or i32 %res1, 305397760
[all …]
/external/libaom/libaom/av1/common/arm/
Dwiener_convolve_neon.c79 int16x8_t res0, res1, res2, res3; in av1_wiener_convolve_add_src_neon() local
119 res1 = vreinterpretq_s16_u16(vaddl_u8(t1, t5)); in av1_wiener_convolve_add_src_neon()
122 res4 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
126 res1 = vreinterpretq_s16_u16(vaddl_u8(t2, t6)); in av1_wiener_convolve_add_src_neon()
129 res5 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
133 res1 = vreinterpretq_s16_u16(vaddl_u8(t3, t7)); in av1_wiener_convolve_add_src_neon()
136 res6 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
140 res1 = vreinterpretq_s16_u16(vaddl_u8(t4, t8)); in av1_wiener_convolve_add_src_neon()
143 res7 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
147 res1 = vreinterpretq_s16_u16(vaddl_u8(t5, t9)); in av1_wiener_convolve_add_src_neon()
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dasm-18.ll161 %res1 = extractvalue { i32, i32 } %res, 0
163 %trunc1 = trunc i32 %res1 to i8
184 %res1 = extractvalue { i32, i32 } %res, 0
186 %trunc1 = trunc i32 %res1 to i16
329 %res1 = call i32 asm "stepa $0", "=h"()
330 %and1 = and i32 %res1, 65535
348 %res1 = call i32 asm "stepa $0", "=r"()
349 %and1 = and i32 %res1, 65535
369 %res1 = call i32 asm "stepa $0", "=h"()
370 %or1 = or i32 %res1, 305397760
[all …]

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