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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  *  tsec.h
4  *
5  *  Driver for the Motorola Triple Speed Ethernet Controller
6  *
7  * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
8  * (C) Copyright 2003, Motorola, Inc.
9  * maintained by Xianghua Xiao (x.xiao@motorola.com)
10  * author Andy Fleming
11  */
12 
13 #ifndef __TSEC_H
14 #define __TSEC_H
15 
16 #include <net.h>
17 #include <config.h>
18 #include <phy.h>
19 
20 #ifndef CONFIG_DM_ETH
21 
22 #ifdef CONFIG_ARCH_LS1021A
23 #define TSEC_SIZE		0x40000
24 #define TSEC_MDIO_OFFSET	0x40000
25 #else
26 #define TSEC_SIZE 		0x01000
27 #define TSEC_MDIO_OFFSET	0x01000
28 #endif
29 
30 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
31 
32 #define TSEC_GET_REGS(num, offset) \
33 	(struct tsec __iomem *)\
34 	(TSEC_BASE_ADDR + (((num) - 1) * (offset)))
35 
36 #define TSEC_GET_REGS_BASE(num) \
37 	TSEC_GET_REGS((num), TSEC_SIZE)
38 
39 #define TSEC_GET_MDIO_REGS(num, offset) \
40 	(struct tsec_mii_mng __iomem *)\
41 	(CONFIG_SYS_MDIO_BASE_ADDR  + ((num) - 1) * (offset))
42 
43 #define TSEC_GET_MDIO_REGS_BASE(num) \
44 	TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
45 
46 #define DEFAULT_MII_NAME "FSL_MDIO"
47 
48 #define STD_TSEC_INFO(num) \
49 {			\
50 	.regs = TSEC_GET_REGS_BASE(num), \
51 	.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
52 	.devname = CONFIG_TSEC##num##_NAME, \
53 	.phyaddr = TSEC##num##_PHY_ADDR, \
54 	.flags = TSEC##num##_FLAGS, \
55 	.mii_devname = DEFAULT_MII_NAME \
56 }
57 
58 #define SET_STD_TSEC_INFO(x, num) \
59 {			\
60 	x.regs = TSEC_GET_REGS_BASE(num); \
61 	x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
62 	x.devname = CONFIG_TSEC##num##_NAME; \
63 	x.phyaddr = TSEC##num##_PHY_ADDR; \
64 	x.flags = TSEC##num##_FLAGS;\
65 	x.mii_devname = DEFAULT_MII_NAME;\
66 }
67 
68 #endif /* CONFIG_DM_ETH */
69 
70 #define MAC_ADDR_LEN		6
71 
72 /* #define TSEC_TIMEOUT	1000000 */
73 #define TSEC_TIMEOUT		1000
74 #define TOUT_LOOP		1000000
75 
76 /* TBI register addresses */
77 #define TBI_CR			0x00
78 #define TBI_SR			0x01
79 #define TBI_ANA			0x04
80 #define TBI_ANLPBPA		0x05
81 #define TBI_ANEX		0x06
82 #define TBI_TBICON		0x11
83 
84 /* TBI MDIO register bit fields*/
85 #define TBICON_CLK_SELECT	0x0020
86 #define TBIANA_ASYMMETRIC_PAUSE	0x0100
87 #define TBIANA_SYMMETRIC_PAUSE	0x0080
88 #define TBIANA_HALF_DUPLEX	0x0040
89 #define TBIANA_FULL_DUPLEX	0x0020
90 #define TBICR_PHY_RESET		0x8000
91 #define TBICR_ANEG_ENABLE	0x1000
92 #define TBICR_RESTART_ANEG	0x0200
93 #define TBICR_FULL_DUPLEX	0x0100
94 #define TBICR_SPEED1_SET	0x0040
95 
96 /* MAC register bits */
97 #define MACCFG1_SOFT_RESET	0x80000000
98 #define MACCFG1_RESET_RX_MC	0x00080000
99 #define MACCFG1_RESET_TX_MC	0x00040000
100 #define MACCFG1_RESET_RX_FUN	0x00020000
101 #define MACCFG1_RESET_TX_FUN	0x00010000
102 #define MACCFG1_LOOPBACK	0x00000100
103 #define MACCFG1_RX_FLOW		0x00000020
104 #define MACCFG1_TX_FLOW		0x00000010
105 #define MACCFG1_SYNCD_RX_EN	0x00000008
106 #define MACCFG1_RX_EN		0x00000004
107 #define MACCFG1_SYNCD_TX_EN	0x00000002
108 #define MACCFG1_TX_EN		0x00000001
109 
110 #define MACCFG2_INIT_SETTINGS	0x00007205
111 #define MACCFG2_FULL_DUPLEX	0x00000001
112 #define MACCFG2_IF		0x00000300
113 #define MACCFG2_GMII		0x00000200
114 #define MACCFG2_MII		0x00000100
115 
116 #define ECNTRL_INIT_SETTINGS	0x00001000
117 #define ECNTRL_TBI_MODE		0x00000020
118 #define ECNTRL_REDUCED_MODE	0x00000010
119 #define ECNTRL_R100		0x00000008
120 #define ECNTRL_REDUCED_MII_MODE	0x00000004
121 #define ECNTRL_SGMII_MODE	0x00000002
122 
123 #ifndef CONFIG_SYS_TBIPA_VALUE
124 # define CONFIG_SYS_TBIPA_VALUE	0x1f
125 #endif
126 
127 #define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN
128 
129 #define MINFLR_INIT_SETTINGS	0x00000040
130 
131 #define DMACTRL_INIT_SETTINGS	0x000000c3
132 #define DMACTRL_GRS		0x00000010
133 #define DMACTRL_GTS		0x00000008
134 #define DMACTRL_LE		0x00008000
135 
136 #define TSTAT_CLEAR_THALT	0x80000000
137 #define RSTAT_CLEAR_RHALT	0x00800000
138 
139 #define IEVENT_INIT_CLEAR	0xffffffff
140 #define IEVENT_BABR		0x80000000
141 #define IEVENT_RXC		0x40000000
142 #define IEVENT_BSY		0x20000000
143 #define IEVENT_EBERR		0x10000000
144 #define IEVENT_MSRO		0x04000000
145 #define IEVENT_GTSC		0x02000000
146 #define IEVENT_BABT		0x01000000
147 #define IEVENT_TXC		0x00800000
148 #define IEVENT_TXE		0x00400000
149 #define IEVENT_TXB		0x00200000
150 #define IEVENT_TXF		0x00100000
151 #define IEVENT_IE		0x00080000
152 #define IEVENT_LC		0x00040000
153 #define IEVENT_CRL		0x00020000
154 #define IEVENT_XFUN		0x00010000
155 #define IEVENT_RXB0		0x00008000
156 #define IEVENT_GRSC		0x00000100
157 #define IEVENT_RXF0		0x00000080
158 
159 #define IMASK_INIT_CLEAR	0x00000000
160 #define IMASK_TXEEN		0x00400000
161 #define IMASK_TXBEN		0x00200000
162 #define IMASK_TXFEN		0x00100000
163 #define IMASK_RXFEN0		0x00000080
164 
165 /* Default Attribute fields */
166 #define ATTR_INIT_SETTINGS	0x000000c0
167 #define ATTRELI_INIT_SETTINGS	0x00000000
168 
169 /* TxBD status field bits */
170 #define TXBD_READY		0x8000
171 #define TXBD_PADCRC		0x4000
172 #define TXBD_WRAP		0x2000
173 #define TXBD_INTERRUPT		0x1000
174 #define TXBD_LAST		0x0800
175 #define TXBD_CRC		0x0400
176 #define TXBD_DEF		0x0200
177 #define TXBD_HUGEFRAME		0x0080
178 #define TXBD_LATECOLLISION	0x0080
179 #define TXBD_RETRYLIMIT		0x0040
180 #define TXBD_RETRYCOUNTMASK	0x003c
181 #define TXBD_UNDERRUN		0x0002
182 #define TXBD_STATS		0x03ff
183 
184 /* RxBD status field bits */
185 #define RXBD_EMPTY		0x8000
186 #define RXBD_RO1		0x4000
187 #define RXBD_WRAP		0x2000
188 #define RXBD_INTERRUPT		0x1000
189 #define RXBD_LAST		0x0800
190 #define RXBD_FIRST		0x0400
191 #define RXBD_MISS		0x0100
192 #define RXBD_BROADCAST		0x0080
193 #define RXBD_MULTICAST		0x0040
194 #define RXBD_LARGE		0x0020
195 #define RXBD_NONOCTET		0x0010
196 #define RXBD_SHORT		0x0008
197 #define RXBD_CRCERR		0x0004
198 #define RXBD_OVERRUN		0x0002
199 #define RXBD_TRUNCATED		0x0001
200 #define RXBD_STATS		0x003f
201 
202 struct txbd8 {
203 	uint16_t status;	/* Status Fields */
204 	uint16_t length;	/* Buffer length */
205 	uint32_t bufptr;	/* Buffer Pointer */
206 };
207 
208 struct rxbd8 {
209 	uint16_t status;	/* Status Fields */
210 	uint16_t length;	/* Buffer Length */
211 	uint32_t bufptr;	/* Buffer Pointer */
212 };
213 
214 struct tsec_rmon_mib {
215 	/* Transmit and Receive Counters */
216 	u32	tr64;		/* Tx/Rx 64-byte Frame Counter */
217 	u32	tr127;		/* Tx/Rx 65-127 byte Frame Counter */
218 	u32	tr255;		/* Tx/Rx 128-255 byte Frame Counter */
219 	u32	tr511;		/* Tx/Rx 256-511 byte Frame Counter */
220 	u32	tr1k;		/* Tx/Rx 512-1023 byte Frame Counter */
221 	u32	trmax;		/* Tx/Rx 1024-1518 byte Frame Counter */
222 	u32	trmgv;		/* Tx/Rx 1519-1522 byte Good VLAN Frame */
223 	/* Receive Counters */
224 	u32	rbyt;		/* Receive Byte Counter */
225 	u32	rpkt;		/* Receive Packet Counter */
226 	u32	rfcs;		/* Receive FCS Error Counter */
227 	u32	rmca;		/* Receive Multicast Packet (Counter) */
228 	u32	rbca;		/* Receive Broadcast Packet */
229 	u32	rxcf;		/* Receive Control Frame Packet */
230 	u32	rxpf;		/* Receive Pause Frame Packet */
231 	u32	rxuo;		/* Receive Unknown OP Code */
232 	u32	raln;		/* Receive Alignment Error */
233 	u32	rflr;		/* Receive Frame Length Error */
234 	u32	rcde;		/* Receive Code Error */
235 	u32	rcse;		/* Receive Carrier Sense Error */
236 	u32	rund;		/* Receive Undersize Packet */
237 	u32	rovr;		/* Receive Oversize Packet */
238 	u32	rfrg;		/* Receive Fragments */
239 	u32	rjbr;		/* Receive Jabber */
240 	u32	rdrp;		/* Receive Drop */
241 	/* Transmit Counters */
242 	u32	tbyt;		/* Transmit Byte Counter */
243 	u32	tpkt;		/* Transmit Packet */
244 	u32	tmca;		/* Transmit Multicast Packet */
245 	u32	tbca;		/* Transmit Broadcast Packet */
246 	u32	txpf;		/* Transmit Pause Control Frame */
247 	u32	tdfr;		/* Transmit Deferral Packet */
248 	u32	tedf;		/* Transmit Excessive Deferral Packet */
249 	u32	tscl;		/* Transmit Single Collision Packet */
250 	/* (0x2_n700) */
251 	u32	tmcl;		/* Transmit Multiple Collision Packet */
252 	u32	tlcl;		/* Transmit Late Collision Packet */
253 	u32	txcl;		/* Transmit Excessive Collision Packet */
254 	u32	tncl;		/* Transmit Total Collision */
255 
256 	u32	res2;
257 
258 	u32	tdrp;		/* Transmit Drop Frame */
259 	u32	tjbr;		/* Transmit Jabber Frame */
260 	u32	tfcs;		/* Transmit FCS Error */
261 	u32	txcf;		/* Transmit Control Frame */
262 	u32	tovr;		/* Transmit Oversize Frame */
263 	u32	tund;		/* Transmit Undersize Frame */
264 	u32	tfrg;		/* Transmit Fragments Frame */
265 	/* General Registers */
266 	u32	car1;		/* Carry Register One */
267 	u32	car2;		/* Carry Register Two */
268 	u32	cam1;		/* Carry Register One Mask */
269 	u32	cam2;		/* Carry Register Two Mask */
270 };
271 
272 struct tsec_hash_regs {
273 	u32	iaddr0;		/* Individual Address Register 0 */
274 	u32	iaddr1;		/* Individual Address Register 1 */
275 	u32	iaddr2;		/* Individual Address Register 2 */
276 	u32	iaddr3;		/* Individual Address Register 3 */
277 	u32	iaddr4;		/* Individual Address Register 4 */
278 	u32	iaddr5;		/* Individual Address Register 5 */
279 	u32	iaddr6;		/* Individual Address Register 6 */
280 	u32	iaddr7;		/* Individual Address Register 7 */
281 	u32	res1[24];
282 	u32	gaddr0;		/* Group Address Register 0 */
283 	u32	gaddr1;		/* Group Address Register 1 */
284 	u32	gaddr2;		/* Group Address Register 2 */
285 	u32	gaddr3;		/* Group Address Register 3 */
286 	u32	gaddr4;		/* Group Address Register 4 */
287 	u32	gaddr5;		/* Group Address Register 5 */
288 	u32	gaddr6;		/* Group Address Register 6 */
289 	u32	gaddr7;		/* Group Address Register 7 */
290 	u32	res2[24];
291 };
292 
293 struct tsec {
294 	/* General Control and Status Registers (0x2_n000) */
295 	u32	res000[4];
296 
297 	u32	ievent;		/* Interrupt Event */
298 	u32	imask;		/* Interrupt Mask */
299 	u32	edis;		/* Error Disabled */
300 	u32	res01c;
301 	u32	ecntrl;		/* Ethernet Control */
302 	u32	minflr;		/* Minimum Frame Length */
303 	u32	ptv;		/* Pause Time Value */
304 	u32	dmactrl;	/* DMA Control */
305 	u32	tbipa;		/* TBI PHY Address */
306 
307 	u32	res034[3];
308 	u32	res040[48];
309 
310 	/* Transmit Control and Status Registers (0x2_n100) */
311 	u32	tctrl;		/* Transmit Control */
312 	u32	tstat;		/* Transmit Status */
313 	u32	res108;
314 	u32	tbdlen;		/* Tx BD Data Length */
315 	u32	res110[5];
316 	u32	ctbptr;		/* Current TxBD Pointer */
317 	u32	res128[23];
318 	u32	tbptr;		/* TxBD Pointer */
319 	u32	res188[30];
320 	/* (0x2_n200) */
321 	u32	res200;
322 	u32	tbase;		/* TxBD Base Address */
323 	u32	res208[42];
324 	u32	ostbd;		/* Out of Sequence TxBD */
325 	u32	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
326 	u32	res2b8[18];
327 
328 	/* Receive Control and Status Registers (0x2_n300) */
329 	u32	rctrl;		/* Receive Control */
330 	u32	rstat;		/* Receive Status */
331 	u32	res308;
332 	u32	rbdlen;		/* RxBD Data Length */
333 	u32	res310[4];
334 	u32	res320;
335 	u32	crbptr;		/* Current Receive Buffer Pointer */
336 	u32	res328[6];
337 	u32	mrblr;		/* Maximum Receive Buffer Length */
338 	u32	res344[16];
339 	u32	rbptr;		/* RxBD Pointer */
340 	u32	res388[30];
341 	/* (0x2_n400) */
342 	u32	res400;
343 	u32	rbase;		/* RxBD Base Address */
344 	u32	res408[62];
345 
346 	/* MAC Registers (0x2_n500) */
347 	u32	maccfg1;	/* MAC Configuration #1 */
348 	u32	maccfg2;	/* MAC Configuration #2 */
349 	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
350 	u32	hafdup;		/* Half-duplex */
351 	u32	maxfrm;		/* Maximum Frame */
352 	u32	res514;
353 	u32	res518;
354 
355 	u32	res51c;
356 
357 	u32	resmdio[6];
358 
359 	u32	res538;
360 
361 	u32	ifstat;		/* Interface Status */
362 	u32	macstnaddr1;	/* Station Address, part 1 */
363 	u32	macstnaddr2;	/* Station Address, part 2 */
364 	u32	res548[46];
365 
366 	/* (0x2_n600) */
367 	u32	res600[32];
368 
369 	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
370 	struct tsec_rmon_mib	rmon;
371 	u32	res740[48];
372 
373 	/* Hash Function Registers (0x2_n800) */
374 	struct tsec_hash_regs	hash;
375 
376 	u32	res900[128];
377 
378 	/* Pattern Registers (0x2_nb00) */
379 	u32	resb00[62];
380 	u32	attr; /* Default Attribute Register */
381 	u32	attreli; /* Default Attribute Extract Length and Index */
382 
383 	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
384 	u32	resc00[256];
385 };
386 
387 #define TSEC_GIGABIT	(1 << 0)
388 
389 /* These flags currently only have meaning if we're using the eTSEC */
390 #define TSEC_REDUCED	(1 << 1)	/* MAC-PHY interface uses RGMII */
391 #define TSEC_SGMII	(1 << 2)	/* MAC-PHY interface uses SGMII */
392 
393 #define TX_BUF_CNT	2
394 
395 struct tsec_private {
396 	struct txbd8 __iomem txbd[TX_BUF_CNT];
397 	struct rxbd8 __iomem rxbd[PKTBUFSRX];
398 	struct tsec __iomem *regs;
399 	struct tsec_mii_mng __iomem *phyregs_sgmii;
400 	struct phy_device *phydev;
401 	phy_interface_t interface;
402 	struct mii_dev *bus;
403 	uint phyaddr;
404 	uint tbiaddr;
405 	char mii_devname[16];
406 	u32 flags;
407 	uint rx_idx;	/* index of the current RX buffer */
408 	uint tx_idx;	/* index of the current TX buffer */
409 #ifndef CONFIG_DM_ETH
410 	struct eth_device *dev;
411 #else
412 	struct udevice *dev;
413 #endif
414 };
415 
416 struct tsec_info_struct {
417 	struct tsec __iomem *regs;
418 	struct tsec_mii_mng __iomem *miiregs_sgmii;
419 	char *devname;
420 	char *mii_devname;
421 	phy_interface_t interface;
422 	unsigned int phyaddr;
423 	u32 flags;
424 };
425 
426 #ifndef CONFIG_DM_ETH
427 int tsec_standard_init(bd_t *bis);
428 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
429 #endif
430 
431 #endif /* __TSEC_H */
432