Searched refs:rhs3 (Results 1 – 7 of 7) sorted by relevance
/external/eigen/test/ |
D | product_symm.cpp | 31 Rhs3 rhs3 = Rhs3::Random(cols, othersize), rhs32(cols, othersize), rhs33(cols, othersize); in symm() local 80 VERIFY_IS_APPROX(rhs12 -= (s1*m2).template selfadjointView<Lower>() * (s2*rhs3), in symm() 81 rhs13 -= (s1*m1) * (s2 * rhs3)); in symm() 84 …VERIFY_IS_APPROX(rhs12 = (s1*m2.adjoint()).template selfadjointView<Lower>() * (s2*rhs3).conjugate… in symm() 85 rhs13 = (s1*m1.adjoint()) * (s2*rhs3).conjugate()); in symm() 89 …rhs12.noalias() += s1 * ((m2.adjoint()).template selfadjointView<Lower>() * (s2*rhs3).conjugate()), in symm() 90 rhs13 += (s1*m1.adjoint()) * (s2*rhs3).conjugate()); in symm()
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D | product_syrk.cpp | 31 Rhs3 rhs3 = Rhs3::Random(internal::random<int>(1,320), rows); in syrk() local 69 VERIFY_IS_APPROX(m2.template selfadjointView<Lower>().rankUpdate(rhs3.adjoint(),s1)._expression(), in syrk() 70 … (s1 * rhs3.adjoint() * rhs3).eval().template triangularView<Lower>().toDenseMatrix()); in syrk() 73 VERIFY_IS_APPROX(m2.template selfadjointView<Upper>().rankUpdate(rhs3.adjoint(),s1)._expression(), in syrk() 74 … (s1 * rhs3.adjoint() * rhs3).eval().template triangularView<Upper>().toDenseMatrix()); in syrk()
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D | svd_common.h | 216 RhsType3 rhs3 = C * rhs2; in svd_min_norm() local 218 SolutionType x3 = svd3.solve(rhs3); in svd_min_norm() 219 VERIFY_IS_APPROX(m3*x3, rhs3); in svd_min_norm() 220 VERIFY_IS_APPROX(m3*x21, rhs3); in svd_min_norm()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | cond-sel.ll | 78 %rhs3 = sext i32 %rhs32 to i64 79 %tst3 = icmp ugt i64 %lhs64, %rhs3 80 %inc3 = add i64 %rhs3, 1 118 %rhs3 = sext i32 %rhs32 to i64 119 %tst3 = icmp ugt i64 %lhs64, %rhs3 120 %inc3 = xor i64 -1, %rhs3 155 %rhs3 = mul i64 %rhs64, 19 156 %tst3 = icmp ugt i64 %lhs64, %rhs3 157 %val3 = select i1 %tst3, i64 %rhs3, i64 -1 186 %rhs3 = sext i32 %rhs32 to i64 [all …]
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D | addsub-shifted.ll | 21 %rhs3 = load volatile i32, i32* @var32 22 %shift3 = shl i32 %rhs3, 5
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/external/llvm/test/CodeGen/AArch64/ |
D | cond-sel.ll | 78 %rhs3 = sext i32 %rhs32 to i64 79 %tst3 = icmp ugt i64 %lhs64, %rhs3 80 %inc3 = add i64 %rhs3, 1 118 %rhs3 = sext i32 %rhs32 to i64 119 %tst3 = icmp ugt i64 %lhs64, %rhs3 120 %inc3 = xor i64 -1, %rhs3 155 %rhs3 = mul i64 %rhs64, 19 156 %tst3 = icmp ugt i64 %lhs64, %rhs3 157 %val3 = select i1 %tst3, i64 %rhs3, i64 -1 186 %rhs3 = sext i32 %rhs32 to i64 [all …]
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D | addsub-shifted.ll | 21 %rhs3 = load volatile i32, i32* @var32 22 %shift3 = shl i32 %rhs3, 5
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