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Searched refs:rlwinm (Results 1 – 25 of 112) sorted by relevance

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/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-ext.s.cs497 0x54,0x62,0x28,0x06 = rlwinm 2, 3, 5, 0, 3
498 0x54,0x62,0x28,0x07 = rlwinm. 2, 3, 5, 0, 3
499 0x54,0x62,0x4f,0x3e = rlwinm 2, 3, 9, 28, 31
500 0x54,0x62,0x4f,0x3f = rlwinm. 2, 3, 9, 28, 31
505 0x54,0x62,0x20,0x3e = rlwinm 2, 3, 4, 0, 31
506 0x54,0x62,0x20,0x3f = rlwinm. 2, 3, 4, 0, 31
507 0x54,0x62,0xe0,0x3e = rlwinm 2, 3, 28, 0, 31
508 0x54,0x62,0xe0,0x3f = rlwinm. 2, 3, 28, 0, 31
512 0x54,0x62,0x20,0x37 = rlwinm. 2, 3, 4, 0, 27
514 0x54,0x62,0xe1,0x3f = rlwinm. 2, 3, 28, 4, 31
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dshift_mask.ll8 ; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31
19 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
30 ; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31
41 ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
92 ; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31
93 ; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31
104 ; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31
105 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
116 ; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31
127 ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
[all …]
Dsetcc-to-sub.ll14 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
15 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
36 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
37 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
59 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
60 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
81 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
82 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
Dfast-isel-fold.ll13 ; ELF64-NOT: rlwinm
23 ; ELF64-NOT: rlwinm
33 ; ELF64-NOT: rlwinm
46 ; ELF64-NOT: rlwinm
55 ; ELF64-NOT: rlwinm
64 ; ELF64-NOT: rlwinm
73 ; ELF64-NOT: rlwinm
Dvec_extract_p9.ll42 ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30
48 ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
61 ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30
67 ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
80 ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29
85 ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
97 ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29
103 ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
Dtail-dup-layout.ll31 ;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
34 ;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 29, 29
37 ;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 28, 28
42 ;CHECK: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
45 ;CHECK: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 29, 29
48 ;CHECK: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 28, 28
122 ;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
125 ;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 29, 29
130 ;CHECK: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
133 ;CHECK: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 29, 29
[all …]
Dandc.ll9 ; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
22 ; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
36 ; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
Dbool-math.ll47 ; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
60 ; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
73 ; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
125 ; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
149 ; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
Dvec_extract_p9_2.ll52 ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30
59 ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
76 ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30
83 ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
100 ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29
107 ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
121 ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29
128 ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
Dbperm.ll12 ; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31
124 ; CHECK: rlwinm [[REG1:[0-9]+]], 3, 16, 24, 31
137 ; CHECK: rlwinm [[REG1:[0-9]+]], 3, 27, 9, 12
210 ; CHECK: rlwinm 3, 3, 0, 1, 0
222 ; CHECK: rlwinm 3, 3, 0, 20, 15
236 ; CHECK: rlwinm 3, 3, 4, 24, 31
Dfunnel-shift-rot.ll21 ; CHECK-NEXT: rlwinm 4, 3, 27, 0, 31
45 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
112 ; CHECK-NEXT: rlwinm 4, 3, 29, 0, 31
123 ; CHECK-NEXT: rlwinm 3, 3, 29, 0, 31
136 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
161 ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
Dzext-bitperm.ll6 ; We expect mask and rotate are folded into a rlwinm instruction.
11 ; CHECK: rlwinm [[REG2:[0-9]+]], [[REG1]], 2, 22, 29
Dtail-dup-break-cfg.ll18 ;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
23 ;CHECK: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
61 ;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
109 ; CHECK: rlwinm. {{[0-9]+}}, {{[0-9]+}}, 0, 29, 29
Datomic-minmax.ll235 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
262 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
289 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
314 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
339 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
365 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
391 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
415 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
DtestComparesi32leu.ll12 ; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
13 ; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
Drlwinm-zero-ext.ll8 ; CHECK-NOT: rlwinm {{{[0-9]+}}}, {{[0-9]+}}, 0, 24, 27
24 ; CHECK: rlwinm [[REG:[0-9]+]], {{[0-9]+}}, 0, 28, 23
/external/llvm/test/CodeGen/PowerPC/
Dfast-isel-fold.ll13 ; ELF64-NOT: rlwinm
23 ; ELF64-NOT: rlwinm
33 ; ELF64-NOT: rlwinm
46 ; ELF64-NOT: rlwinm
55 ; ELF64-NOT: rlwinm
64 ; ELF64-NOT: rlwinm
73 ; ELF64-NOT: rlwinm
Drlwinm-zero-ext.ll8 ; CHECK-NOT: rlwinm {{{[0-9]+}}}, {{[0-9]+}}, 0, 24, 27
9 ; CHECK: rlwinm. [[REG:[0-9]+]], {{[0-9]+}}, 0, 24, 27
24 ; CHECK: rlwinm [[REG:[0-9]+]], {{[0-9]+}}, 0, 28, 23
Dbperm.ll12 ; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31
124 ; CHECK: rlwinm [[REG1:[0-9]+]], 3, 16, 24, 31
137 ; CHECK: rlwinm [[REG1:[0-9]+]], 3, 27, 9, 12
210 ; CHECK: rlwinm 3, 3, 0, 1, 0
222 ; CHECK: rlwinm 3, 3, 0, 20, 15
236 ; CHECK: rlwinm 3, 3, 4, 24, 31
Dbitreverse.ll10 ; CHECK: rlwinm
19 ; CHECK: rlwinm
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Drelease.S66 rlwinm r3,r3,0,0xff
170 rlwinm r8,r0,29,0x03 /* r8 = core within cluster */
177 rlwinm r4,r0,27,27,31
214 rlwinm r6,r3,24,~0x800 /* clear E bit */
221 rlwinm r3,r3,0,0xf0
256 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
294 rlwinm r13,r13,0,0,19
430 rlwinm r12,r4,0,0,5
/external/u-boot/arch/powerpc/lib/
Dppcstring.S80 rlwinm r0,r5,32-2,2,31
102 rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
137 rlwinm. r7,r5,32-3,3,31
144 rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
174 rlwinm. r7,r5,32-3,3,31
/external/u-boot/arch/powerpc/cpu/mpc86xx/
Drelease.S32 rlwinm r0,r0,27,31,31
76 rlwinm. r3, r3, 0, 0, 0
80 rlwinm r3, r3, 0, 1, 31
/external/llvm/test/MC/PowerPC/
Dppc64-encoding.s704 # CHECK-BE: rlwinm 2, 3, 4, 5, 6 # encoding: [0x54,0x62,0x21,0x4c]
705 # CHECK-LE: rlwinm 2, 3, 4, 5, 6 # encoding: [0x4c,0x21,0x62,0x54]
706 rlwinm 2, 3, 4, 5, 6
707 # CHECK-BE: rlwinm. 2, 3, 4, 5, 6 # encoding: [0x54,0x62,0x21,0x4d]
708 # CHECK-LE: rlwinm. 2, 3, 4, 5, 6 # encoding: [0x4d,0x21,0x62,0x54]
709 rlwinm. 2, 3, 4, 5, 6
761 # CHECK-BE: rlwinm 0, 0, 30, 31, 31 # encoding: [0x54,0x00,0xf7,0xfe]
762 rlwinm 0, 0, 30, 1
763 # CHECK-BE: rlwinm. 0, 0, 30, 31, 31 # encoding: [0x54,0x00,0xf7,0xff]
764 rlwinm. 0, 0, 30, 1
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
D2010-02-12-saveCR.ll10 ;CHECK: rlwinm r2, r2, 8, 0, 31
25 ;CHECK: rlwinm r2, r2, 24, 0, 31

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