| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | dp2.ll | 16 ; CHECK: {{ror|rorv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
103 ; CHECK: {{ror|rorv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
| D | arm64-regress-interphase-shift.ll | 13 ; CHECK: rorv
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | dp2.ll | 16 ; CHECK: {{ror|rorv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
103 ; CHECK: {{ror|rorv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
| D | arm64-regress-interphase-shift.ll | 13 ; CHECK: rorv
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-xfail-mips64r3.txt | 70 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-xfail-mips64r3.txt | 72 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-xfail-mips64r5.txt | 70 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-xfail-mips64r2.txt | 72 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-xfail-mips64r5.txt | 72 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-xfail-mips64r2.txt | 70 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-xfail-mips32r3.txt | 73 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-xfail-mips32r5.txt | 73 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-xfail-mips32r2.txt | 73 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-xfail-mips32r2.txt | 75 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-xfail-mips32r5.txt | 75 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-xfail-mips32r3.txt | 75 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 406 rorv w1, w2, w3
407 rorv x1, x2, x3
|
| D | basic-a64-instructions.s | 1526 rorv w0, w1, w2
1527 rorv x3, x4, x5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 406 rorv w1, w2, w3
407 rorv x1, x2, x3
|
| D | basic-a64-instructions.s | 1509 rorv w0, w1, w2
1510 rorv x3, x4, x5
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 864 rorv(rd, rn, rm); in Ror()
|
| D | assembler-arm64.h | 1360 void rorv(const Register& rd, const Register& rn, const Register& rm);
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 721 void rorv(const Register& rd, const Register& rn, const Register& rm);
|
| D | macro-assembler-aarch64.h | 2134 rorv(rd, rn, rm); in Ror()
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 276 __ rorv(w26, w27, w28); in GenerateTestSequenceBase() local
277 __ rorv(x29, x2, x3); in GenerateTestSequenceBase() local
|