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Searched refs:rri (Results 1 – 25 of 36) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/TableGen/
Dusevalname.td19 def rri : Instr<[(set RC:$dst, (shufp:$src3
/external/llvm/test/TableGen/
Dusevalname.td19 def rri : Instr<[(set RC:$dst, (shufp:$src3
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
Dusevalname.td19 def rri : Instr<[(set RC:$dst, (shufp:$src3
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp706 CASE_SHUF(PALIGNR, rri) in EmitAnyX86InstComments()
720 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri) in EmitAnyX86InstComments()
721 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri) in EmitAnyX86InstComments()
722 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri) in EmitAnyX86InstComments()
738 CASE_AVX512_INS_COMMON(ALIGND, Z, rri) in EmitAnyX86InstComments()
739 CASE_AVX512_INS_COMMON(ALIGND, Z256, rri) in EmitAnyX86InstComments()
740 CASE_AVX512_INS_COMMON(ALIGND, Z128, rri) in EmitAnyX86InstComments()
912 CASE_SHUF(SHUFPD, rri) in EmitAnyX86InstComments()
925 CASE_SHUF(SHUFPS, rri) in EmitAnyX86InstComments()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dshfl-sync.ll35 ; CHECK-LABEL: .func{{.*}}shfl.sync.rri
36 define i32 @shfl.sync.rri(i32 %mask, i32 %a, i32 %b) {
/external/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/
Dp5-0x.cpp119 int&& rri = static_cast<int&&>(i);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86SchedSkylakeServer.td642 "VPBLENDD(Y?)rri",
649 "VPTERNLOGD(Z|Z128|Z256)rri",
650 "VPTERNLOGQ(Z|Z128|Z256)rri")>;
804 "VALIGND(Z|Z128|Z256)rri",
805 "VALIGNQ(Z|Z128|Z256)rri",
806 "VCMPPD(Z|Z128|Z256)rri",
807 "VCMPPS(Z|Z128|Z256)rri",
817 "VPCMPB(Z|Z128|Z256)rri",
818 "VPCMPD(Z|Z128|Z256)rri",
822 "VPCMPQ(Z|Z128|Z256)rri",
[all …]
DX86InstrMMX.td115 def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
DX86InstrAVX512.td2279 def rri : AVX512AIi8<opc, MRMSrcReg,
2533 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
9853 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
9913 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
9944 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
9985 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
10145 (!cast<Instruction>("VRNDSCALE"#Suffix#_.ZSuffix#"rri")
10148 (!cast<Instruction>("VRNDSCALE"#Suffix#_.ZSuffix#"rri")
10151 (!cast<Instruction>("VRNDSCALE"#Suffix#_.ZSuffix#"rri")
10154 (!cast<Instruction>("VRNDSCALE"#Suffix#_.ZSuffix#"rri")
[all …]
DX86InstrSSE.td1998 def rri : PIi8<0xC2, MRMSrcReg,
2113 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4830 def rri : SS3AI<0x0F, MRMSrcReg, (outs RC:$dst),
6106 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6134 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6224 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7521 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8208 def rri : Ii8<Op, MRMSrcReg, (outs RC:$dst),
DX86SchedSkylakeClient.td626 "VPBLENDD(Y?)rri",
DX86SchedBroadwell.td623 def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>;
DX86SchedHaswell.td915 def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>;
DX86InstrInfo.td2691 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
2708 def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp566 CASE_SHUF(PALIGNR, rri) in EmitAnyX86InstComments()
723 CASE_SHUF(SHUFPD, rri) in EmitAnyX86InstComments()
736 CASE_SHUF(SHUFPS, rri) in EmitAnyX86InstComments()
/external/kernel-headers/original/uapi/asm-mips/asm/
Dinst.h1100 struct m16e_rri rri; member
/external/llvm/lib/Target/X86/
DX86SchedHaswell.td1339 def : InstRW<[WritePBLENDWr], (instregex "(V?)PBLENDW(Y?)rri")>;
1352 def : InstRW<[WriteVPBLENDDr], (instregex "VPBLENDD(Y?)rri")>;
1979 def : InstRW<[WriteDPPSr], (instregex "(V?)DPPS(Y?)rri")>;
DX86InstrAVX512.td1559 def rri : AVX512AIi8<opc, MRMSrcReg,
1718 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
7004 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7058 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7087 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
7124 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
7322 def NAME#_.VTName#rri:
7324 (!cast<Instruction>(NAME#_.ZSuffix#rri)
7716 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7762 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
[all …]
DX86InstrSSE.td2449 def rri : PIi8<0xC2, MRMSrcReg,
2547 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4528 def rri : Ii8<0xC4, MRMSrcReg,
5675 def rri : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
6883 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6911 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
8255 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td1209 def : InstRW<[FalkorWr_2XYZ_2cyc], (instregex "^EXTR(W|X)rri$")>;
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td894 def rri : NVPTXInst<(outs RC:$dst),
1234 def rri
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td993 def rri : NVPTXInst<(outs RC:$dst),
1356 def rri
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrSSE.td2098 def rri : PIi8<0xC2, MRMSrcReg,
2189 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3979 def rri : Ii8<0xC4, MRMSrcReg,
5849 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
DX86GenAsmWriter.inc5887 "6rri\000IMUL16rri8\000IMUL32m\000IMUL32r\000IMUL32rm\000IMUL32rmi\000IM"
/external/cldr/tools/java/org/unicode/cldr/util/data/languages/
DentityToCode.tsv314 http://www.wikidata.org/entity/Q2404190 rri

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