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Searched refs:rshrn2 (Results 1 – 25 of 40) sorted by relevance

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/external/capstone/suite/MC/AArch64/
Dneon-simd-shift.s.cs107 0x20,0x8c,0x0d,0x4f = rshrn2 v0.16b, v1.8h, #3
108 0x20,0x8c,0x1d,0x4f = rshrn2 v0.8h, v1.4s, #3
109 0x20,0x8c,0x3d,0x4f = rshrn2 v0.4s, v1.2d, #3
/external/libjpeg-turbo/simd/arm64/
Djsimd_neon.S734 …rshrn2 v2.8h, v16.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int)DESCALE(tmp13 …
735 …rshrn2 v3.8h, v28.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int)DESCALE(tmp12 …
736 …rshrn2 v4.8h, v24.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*6] = (int)DESCALE(tmp11 …
737 …rshrn2 v5.8h, v20.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*7] = (int)DESCALE(tmp10 …
818 …rshrn2 v6.8h, v17.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int)DESCALE(tmp13 …
819 …rshrn2 v7.8h, v29.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int)DESCALE(tmp12 …
820 …rshrn2 v8.8h, v25.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*6] = (int)DESCALE(tmp11 …
821 …rshrn2 v9.8h, v21.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*7] = (int)DESCALE(tmp10 …
932 …rshrn2 v2.8h, v16.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int)DESCALE(tmp13 …
933 …rshrn2 v3.8h, v28.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int)DESCALE(tmp12 …
[all …]
/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s299 rshrn2 v0.16b, v1.8h, #3
300 rshrn2 v0.8h, v1.4s, #3
301 rshrn2 v0.4s, v1.2d, #3
Darm64-advsimd.s1458 rshrn2.16b v0, v0, #2
1460 rshrn2.8h v0, v0, #4
1462 rshrn2.4s v0, v0, #6
1630 ; CHECK: rshrn2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x4f]
1632 ; CHECK: rshrn2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x4f]
1634 ; CHECK: rshrn2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x4f]
1799 rshrn2 v8.16b, v9.8h, #2
1801 rshrn2 v6.8h, v7.4s, #4
1803 rshrn2 v4.4s, v5.2d, #6
1870 ; CHECK: rshrn2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x4f]
[all …]
Dneon-diagnostics.s1868 rshrn2 v0.16b, v1.8h, #17
1869 rshrn2 v0.8h, v1.4s, #33
1870 rshrn2 v0.4s, v1.2d, #65
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-simd-shift.s299 rshrn2 v0.16b, v1.8h, #3
300 rshrn2 v0.8h, v1.4s, #3
301 rshrn2 v0.4s, v1.2d, #3
Darm64-advsimd.s1458 rshrn2.16b v0, v0, #2
1460 rshrn2.8h v0, v0, #4
1462 rshrn2.4s v0, v0, #6
1630 ; CHECK: rshrn2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x4f]
1632 ; CHECK: rshrn2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x4f]
1634 ; CHECK: rshrn2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x4f]
1799 rshrn2 v8.16b, v9.8h, #2
1801 rshrn2 v6.8h, v7.4s, #4
1803 rshrn2 v4.4s, v5.2d, #6
1870 ; CHECK: rshrn2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x4f]
[all …]
Dneon-diagnostics.s1873 rshrn2 v0.16b, v1.8h, #17
1874 rshrn2 v0.8h, v1.4s, #33
1875 rshrn2 v0.4s, v1.2d, #65
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-simd-shift.ll368 ; CHECK: rshrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
379 ; CHECK: rshrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
390 ; CHECK: rshrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
Darm64-vecFold.ll98 ; CHECK-NEXT: rshrn2.16b v0, v2, #6
Darm64-vshift.ll645 ;CHECK: rshrn2.16b v0, {{v[0-9]+}}, #1
655 ;CHECK: rshrn2.8h v0, {{v[0-9]+}}, #1
665 ;CHECK: rshrn2.4s v0, {{v[0-9]+}}, #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-simd-shift.ll368 ; CHECK: rshrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
379 ; CHECK: rshrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
390 ; CHECK: rshrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
Darm64-vecFold.ll98 ; CHECK-NEXT: rshrn2.16b v0, v2, #6
Darm64-vshift.ll645 ;CHECK: rshrn2.16b v0, {{v[0-9]+}}, #1
655 ;CHECK: rshrn2.8h v0, {{v[0-9]+}}, #1
665 ;CHECK: rshrn2.4s v0, {{v[0-9]+}}, #1
/external/v8/src/arm64/
Dsimulator-logic-arm64.cc2136 LogicVRegister Simulator::rshrn2(VectorFormat vform, LogicVRegister dst, in rshrn2() function in v8::internal::Simulator
2247 return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqrshrn2()
2787 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in raddhn2()
2823 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in rsubhn2()
Dmacro-assembler-arm64.h1044 V(rshrn2, Rshrn2) \
Dsimulator-arm64.h1800 LogicVRegister rshrn2(VectorFormat vform, LogicVRegister dst,
/external/vixl/src/aarch64/
Dlogic-aarch64.cc2607 LogicVRegister Simulator::rshrn2(VectorFormat vform, in rshrn2() function in vixl::aarch64::Simulator
2750 return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqrshrn2()
3514 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in raddhn2()
3558 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in rsubhn2()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2033 # CHECK: rshrn2.16b v0, v0, #0x6
2035 # CHECK: rshrn2.8h v0, v0, #0xc
2037 # CHECK: rshrn2.4s v0, v0, #0x1a
Dneon-instructions.txt989 # CHECK: rshrn2 v0.16b, v1.8h, #3
990 # CHECK: rshrn2 v0.8h, v1.4s, #3
991 # CHECK: rshrn2 v0.4s, v1.2d, #3
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2033 # CHECK: rshrn2.16b v0, v0, #0x6
2035 # CHECK: rshrn2.8h v0, v0, #0xc
2037 # CHECK: rshrn2.4s v0, v0, #0x1a
Dneon-instructions.txt989 # CHECK: rshrn2 v0.16b, v1.8h, #3
990 # CHECK: rshrn2 v0.8h, v1.4s, #3
991 # CHECK: rshrn2 v0.4s, v1.2d, #3
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1107 0x~~~~~~~~~~~~~~~~ 4f088cc3 rshrn2 v3.16b, v6.8h, #8
1108 0x~~~~~~~~~~~~~~~~ 4f278fa0 rshrn2 v0.4s, v29.2d, #25
1109 0x~~~~~~~~~~~~~~~~ 4f118f5b rshrn2 v27.8h, v26.4s, #15
Dlog-disasm1107 0x~~~~~~~~~~~~~~~~ 4f088cc3 rshrn2 v3.16b, v6.8h, #8
1108 0x~~~~~~~~~~~~~~~~ 4f278fa0 rshrn2 v0.4s, v29.2d, #25
1109 0x~~~~~~~~~~~~~~~~ 4f118f5b rshrn2 v27.8h, v26.4s, #15
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1340 __ rshrn2(v3.V16B(), v6.V8H(), 8); in GenerateTestSequenceNEON() local
1341 __ rshrn2(v0.V4S(), v29.V2D(), 25); in GenerateTestSequenceNEON() local
1342 __ rshrn2(v27.V8H(), v26.V4S(), 15); in GenerateTestSequenceNEON() local

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