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Searched refs:rsrc1 (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_pipeline_cache.c37 uint32_t rsrc1, rsrc2; member
313 variant->rsrc1 = info.rsrc1; in radv_create_shader_variants_from_pipeline_cache()
393 info.rsrc1 = variants[i]->rsrc1; in radv_pipeline_cache_insert_shaders()
Dradv_shader.c383 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | in radv_fill_shader_variant()
448 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); in radv_fill_shader_variant()
453 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt); in radv_fill_shader_variant()
455 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt); in radv_fill_shader_variant()
Dradv_shader.h51 unsigned rsrc1; member
Dradv_cmd_buffer.c741 radeon_emit(cmd_buffer->cs, shader->rsrc1); in radv_emit_hw_vs()
769 radeon_emit(cmd_buffer->cs, shader->rsrc1); in radv_emit_hw_es()
790 radeon_emit(cmd_buffer->cs, shader->rsrc1); in radv_emit_hw_ls()
806 radeon_emit(cmd_buffer->cs, shader->rsrc1); in radv_emit_hw_hs()
813 radeon_emit(cmd_buffer->cs, shader->rsrc1); in radv_emit_hw_hs()
954 radeon_emit(cmd_buffer->cs, gs->rsrc1); in radv_emit_geometry_shader()
964 radeon_emit(cmd_buffer->cs, gs->rsrc1); in radv_emit_geometry_shader()
1002 radeon_emit(cmd_buffer->cs, ps->rsrc1); in radv_emit_fragment_shader()
2650 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1); in radv_emit_compute_pipeline()
Dradv_device.c1675 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | in radv_get_preamble_cs() local
1678 map[1] = rsrc1; in radv_get_preamble_cs()
1764 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | in radv_get_preamble_cs() local
1771 radeon_emit(cs, rsrc1); in radv_get_preamble_cs()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute.c72 uint32_t rsrc1 = code_object->compute_pgm_resource_registers; in code_object_to_config() local
76 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1); in code_object_to_config()
77 out_config->rsrc1 = rsrc1; in code_object_to_config()
124 shader->config.rsrc1 = in si_create_compute_state_async()
456 radeon_emit(cs, config->rsrc1); in si_switch_compute_shader()
460 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2); in si_switch_compute_shader()
Dsi_shader.h564 unsigned rsrc1; member
Dsi_state_draw.c283 radeon_emit(cs, ls_current->config.rsrc1); in si_emit_derived_tess_state()
Dsi_state_shaders.c467 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_shader_ls()
Dsi_shader.c5176 conf->rsrc1 = value; in si_shader_binary_read_config()