Home
last modified time | relevance | path

Searched refs:rstctl (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dfsl_lsch2_serdes.c200 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
203 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
206 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
208 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
216 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
219 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
222 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
224 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
263 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
265 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
[all …]
Dfsl_lsch3_serdes.c254 clrbits_le32(&serdes_base->bank[i].rstctl, in do_pll_reset()
258 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_reset()
290 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_reset_done()
302 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN); in do_serdes_enable()
305 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B); in do_serdes_enable()
322 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_lock()
326 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_lock()
/external/u-boot/board/freescale/b4860qds/
Db4860qds.c604 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
607 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
610 setbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
612 setbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
619 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) & in calibrate_pll()
654 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in check_pll_locks()
679 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in check_pll_locks()
711 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in check_pll_locks()
876 clrbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
879 clrbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dfsl_corenet_serdes.c114 if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) in serdes_lane_enabled()
467 u32 rstctl; in wait_for_rstdone() local
472 rstctl = in_be32(&srds_regs->bank[bank].rstctl); in wait_for_rstdone()
473 if (rstctl & SRDS_RSTCTL_RSTDONE) in wait_for_rstdone()
477 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) in wait_for_rstdone()
603 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); in fsl_serdes_init()
644 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
647 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
863 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, in fsl_serdes_init()
/external/u-boot/arch/arm/mach-tegra/
Dlowlevel_init.S28 ldr r1, rstctl @ get addr for global reset
36 rstctl: label
/external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
Dimmap_lsch3.h396 u32 rstctl; /* Reset Control Register */ member
Dimmap_lsch2.h542 u32 rstctl; /* Reset Control Register */ member
/external/u-boot/arch/powerpc/cpu/mpc8xxx/
Dsrio.c92 if (in_be32((void *)&srds_regs->bank[0].rstctl) in srio_erratum_a004034()
/external/u-boot/arch/arm/include/asm/arch-ls102xa/
Dimmap_ls102xa.h341 u32 rstctl; /* Reset Control Register */ member
/external/u-boot/arch/powerpc/include/asm/
Dimmap_85xx.h2533 u32 rstctl; /* Reset Control Register */ member
2621 u32 rstctl; /* Reset Control Register */ member