| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | data.s | 6 v_mov_b32 v7, s24
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceRegistersARM32.def | 61 X(Reg_s24, 24, "s24", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s24, d12, q6)) \
84 X(Reg_d12, 12, "d12", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d12, q6, s24, s25)) \
113 …X(Reg_q6, 6, "q6", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q6, d12, d13, s24, s25, s26…
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-scalar-abs.s.cs | 3 0x1d,0xd7,0xb4,0x7e = fabd s29, s24, s20
|
| D | neon-scalar-mul.s.cs | 9 0x13,0x93,0xac,0x5e = sqdmlal d19, s24, s12
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-abs.s | 18 fabd s29, s24, s20
|
| D | neon-scalar-mul.s | 42 sqdmlal d19, s24, s12
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | neon-scalar-abs.s | 18 fabd s29, s24, s20
|
| D | neon-scalar-mul.s | 42 sqdmlal d19, s24, s12
|
| /external/clang/test/CXX/lex/lex.charset/ |
| D | p2-cxx98.cpp | 36 const char *s24 = "\u0024"; // $, ok variable
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | spill-fold.ll | 63 …3},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s2…
73 …3},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s2…
|
| D | remat-float0.ll | 15 …3},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s2…
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | remat-float0.ll | 15 …3},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s2…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | thumb-fp-armv8.s | 99 vrintz.f32 s3, s24
100 @ CHECK: vrintz.f32 s3, s24 @ encoding: [0xf6,0xee,0xcc,0x1a]
|
| D | fp-armv8.s | 96 vrintz.f32 s3, s24
97 @ CHECK: vrintz.f32 s3, s24 @ encoding: [0xcc,0x1a,0xf6,0xee]
|
| D | fullfp16.s | 169 vrintz.f16 s3, s24
170 @ ARM: vrintz.f16 s3, s24 @ encoding: [0xcc,0x19,0xf6,0xee]
171 @ THUMB: vrintz.f16 s3, s24 @ encoding: [0xf6,0xee,0xcc,0x19]
|
| /external/llvm/test/MC/ARM/ |
| D | fp-armv8.s | 96 vrintz.f32 s3, s24
97 @ CHECK: vrintz.f32 s3, s24 @ encoding: [0xcc,0x1a,0xf6,0xee]
|
| D | thumb-fp-armv8.s | 99 vrintz.f32 s3, s24
100 @ CHECK: vrintz.f32 s3, s24 @ encoding: [0xf6,0xee,0xcc,0x1a]
|
| D | fullfp16.s | 169 vrintz.f16 s3, s24
170 @ ARM: vrintz.f16 s3, s24 @ encoding: [0xcc,0x19,0xf6,0xee]
171 @ THUMB: vrintz.f16 s3, s24 @ encoding: [0xf6,0xee,0xcc,0x19]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | spill-alloc-sgpr-init-bug.ll | 19 call void asm sideeffect "", "~{s4},~{s8},~{s12},~{s16},~{s20},~{s24},~{s28}" ()
|
| D | branch-relax-spill.ll | 34 %sgpr24 = tail call i32 asm sideeffect "s_mov_b32 s24, 0", "={s24}"() #0
153 tail call void asm sideeffect "; reg use $0", "{s24}"(i32 %sgpr24) #0
|
| /external/capstone/suite/MC/ARM/ |
| D | thumb-fp-armv8.s.cs | 39 0xf6,0xee,0xcc,0x1a = vrintz.f32 s3, s24
|
| D | fp-armv8.s.cs | 39 0xcc,0x1a,0xf6,0xee = vrintz.f32 s3, s24
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/ARM/ |
| D | split-superreg-piece.mir | 81 '$s23', '$s24', '$s25', '$s26', '$s27', '$s28',
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-fp-armv8.txt | 124 # CHECK: vrintz.f32 s3, s24
|
| D | fp-armv8.txt | 119 # CHECK: vrintz.f32 s3, s24
|