| /external/capstone/suite/MC/AArch64/ |
| D | neon-scalar-by-elem-saturating-mul.s.cs | 12 0x59,0xcb,0xbb,0x5f = sqdmulh s25, s26, v27.s[3]
18 0x54,0xd3,0xbb,0x5f = sqrdmulh s20, s26, v27.s[1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | neon-scalar-by-elem-saturating-mul.s | 30 sqdmulh s25, s26, v27.s[3]
47 sqrdmulh s20, s26, v27.s[1]
|
| D | basic-a64-diagnostics.s | 2664 ldp s6, s26, [x4, #-260]
2775 ldp s6, s26, [x4], #-260
2886 ldp s6, s26, [x4, #-260]!
2984 ldnp s6, s26, [x4, #-260]
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-by-elem-saturating-mul.s | 30 sqdmulh s25, s26, v27.s[3]
47 sqrdmulh s20, s26, v27.s[1]
|
| D | basic-a64-diagnostics.s | 2575 ldp s6, s26, [x4, #-260]
2678 ldp s6, s26, [x4], #-260
2781 ldp s6, s26, [x4, #-260]!
2870 ldnp s6, s26, [x4, #-260]
|
| /external/llvm/test/MC/ARM/ |
| D | d16.s | 23 @ D16-NEXT: vcvt.f32.f64 s26, d30
24 vcvt.f32.f64 s26, d30
|
| D | simple-fp-encoding.s | 323 @ CHECK: vmovne s25, s26, r2, r5
324 vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | d16.s | 25 @ D16-NEXT: vcvt.f32.f64 s26, d30
26 vcvt.f32.f64 s26, d30
|
| D | simple-fp-encoding.s | 335 @ CHECK: vmovne s25, s26, r2, r5
336 vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c]
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceRegistersARM32.def | 63 X(Reg_s26, 26, "s26", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s26, d13, q6)) \
85 X(Reg_d13, 13, "d13", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d13, q6, s26, s27)) \
113 …, 6, "q6", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q6, d12, d13, s24, s25, s26, s27)) \
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | spill-fold.ll | 63 …5},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s2…
73 …5},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s2…
|
| D | remat-float0.ll | 15 …5},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s2…
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | remat-float0.ll | 15 …5},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s2…
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | d16.txt | 21 # D32: vcvt.f32.f64 s26, d30
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | d16.txt | 21 # D32: vcvt.f32.f64 s26, d30
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | simple-fp-encoding.s | 244 @ CHECK: vmovne s25, s26, r2, r5
245 vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c]
|
| /external/clang/test/CodeGen/ |
| D | x86_32-arguments-darwin.c | 120 struct s26 { struct { char a, b; } a; struct { char a, b; } b; } f26(void) { while (1) {} } in f26() argument
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | branch-relax-spill.ll | 36 %sgpr26 = tail call i32 asm sideeffect "s_mov_b32 s26, 0", "={s26}"() #0
155 tail call void asm sideeffect "; reg use $0", "{s26}"(i32 %sgpr26) #0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/ARM/ |
| D | split-superreg-piece.mir | 81 '$s23', '$s24', '$s25', '$s26', '$s27', '$s28',
|
| D | split-superreg.mir | 81 '$s23', '$s24', '$s25', '$s26', '$s27', '$s28',
|
| D | split-superreg-complex.mir | 81 '$s23', '$s24', '$s25', '$s26', '$s27', '$s28',
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/ |
| D | tbb-reuse.mir | 71 '$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
|
| /external/v8/src/arm/ |
| D | simulator-arm.h | 75 s24, s25, s26, s27, s28, s29, s30, s31, enumerator
|
| /external/llvm/test/CodeGen/MIR/ARM/ |
| D | ARMLoadStoreDBG.mir | 96 '%s22', '%s23', '%s24', '%s25', '%s26', '%s27',
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | ARMLoadStoreDBG.mir | 92 '$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
|