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Searched refs:s_add_u32 (Results 1 – 25 of 79) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dtrap.s15 s_add_u32 ttmp0, ttmp0, 4 label
20 s_add_u32 ttmp4, 8, ttmp4 label
25 s_add_u32 ttmp4, ttmp4, 0x00000100 label
30 s_add_u32 ttmp4, ttmp4, 4 label
35 s_add_u32 ttmp4, ttmp8, ttmp4 label
127 s_add_u32 ttmp0, ttmp12, 4 label
131 s_add_u32 ttmp0, ttmp13, 4 label
135 s_add_u32 ttmp0, ttmp14, 4 label
139 s_add_u32 ttmp0, ttmp15, 4 label
Dsop2.s13 s_add_u32 s1, s2, s3 label
181 s_add_u32 s101, s102, s103 label
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dglobal-variable-relocs.ll17 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], private@rel32@lo+8
31 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], internal@rel32@lo+8
45 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], available_externally@gotpcrel32@lo+4
48 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
62 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce@gotpcrel32@lo+4
65 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
79 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak@gotpcrel32@lo+4
82 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
96 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], common@gotpcrel32@lo+4
99 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
[all …]
Dstack-realign.ll32 ; GCN: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0x3c0{{$}}
34 ; GCN: s_add_u32 s32, s32, 0x2800{{$}}
53 ; GCN: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0x7c0{{$}}
55 ; GCN: s_add_u32 s32, s32, 0x3000{{$}}
74 ; GCN: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0xc0{{$}}
76 ; GCN: s_add_u32 s32, s32, 0xd00{{$}}
90 ; GCN: s_add_u32 s32, s8, 0x400{{$}}
102 ; GCN: s_add_u32 s32, s8, 0x400
113 ; GCN: s_add_u32 s32, s8, 0x400
Dspill-wide-sgpr.ll6 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
10 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
47 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
51 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
96 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
98 ; SMEM: s_add_u32 m0, s3, 0x110{{$}}
102 ; SMEM: s_add_u32 m0, s3, 0x100{{$}}
104 ; SMEM: s_add_u32 m0, s3, 0x110{{$}}
Dglobal-constant.ll12 ; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1
16 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4
22 ; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
26 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4
41 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4
Dspill-m0.ll23 ; TOSMEM: s_add_u32 m0, s3, 0x100{{$}}
38 ; TOSMEM: s_add_u32 m0, s3, 0x100{{$}}
68 ; TOSMEM: s_add_u32 m0, s7, 0x100
74 ; TOSMEM: s_add_u32 m0, s7, 0x300
83 ; TOSMEM: s_add_u32 m0, s7, 0x400
124 ; TOSMEM: s_add_u32 m0, s3, 0x100
133 ; TOSMEM: s_add_u32 m0, s3, 0x100
164 ; TOSMEM: s_add_u32 m0, s3, 0x100
167 ; TOSMEM: s_add_u32 m0, s3, 0x300
175 ; TOSMEM: s_add_u32 m0, s3, 0x100
[all …]
Dmem-builtins.ll14 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, memcmp@rel32@lo+4
25 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, memchr@rel32@lo+4
35 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcpy@rel32@lo+4
45 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcmp@rel32@lo+4
55 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strlen@rel32@lo+4
65 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strnlen@rel32@lo+4
Dbranch-relax-bundle.ll11 ; s_add_u32
23 ; GCN-NEXT: s_add_u32
29 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, func@
Dadd_i64.ll22 ; SI: s_add_u32
35 ; SI: s_add_u32
46 ; SI: s_add_u32
48 ; SI: s_add_u32
Dcall-argument-types.ll65 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1@rel32@lo+4
82 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_signext@rel32@lo+4
106 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_zeroext@rel32@lo+4
127 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8@rel32@lo+4
148 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext@rel32@lo+4
169 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext@rel32@lo+4
201 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_signext@rel32@lo+4
222 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_zeroext@rel32@lo+4
241 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i32@rel32@lo+4
259 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i64@rel32@lo+4
[all …]
Dadd_i128.ll22 ; GCN: s_add_u32
34 ; GCN: s_add_u32
46 ; GCN: s_add_u32
Dcall-preserved-registers.ll10 ; GCN-NEXT: s_add_u32 s34, s34,
94 ; GCN-NEXT: s_add_u32
135 ; GCN-NEXT: s_add_u32 s6, s6, external_void_func_void@rel32@lo+4
156 ; GCN-NEXT: s_add_u32 s6, s6, external_void_func_void@rel32@lo+4
187 ; GCN-NEXT: s_add_u32
Dbranch-relaxation.ll65 ; GCN-NEXT: s_add_u32 vcc_lo, vcc_lo, [[ENDBB:BB[0-9]+_[0-9]+]]-([[LONG_JUMP]]+4)
109 ; GCN-NEXT: s_add_u32 vcc_lo, vcc_lo, [[ENDBB:BB[0-9]+_[0-9]+]]-([[LONG_JUMP]]+4)
229 ; GCN-NEXT: s_add_u32 vcc_lo, vcc_lo, [[BB3:BB[0-9]_[0-9]+]]-([[LONG_JUMP0]]+4)
239 ; GCN-NEXT: s_add_u32 vcc_lo, vcc_lo, [[BB4:BB[0-9]_[0-9]+]]-([[LONG_JUMP1]]+4)
322 ; GCN-NEXT: s_add_u32 vcc_lo, vcc_lo, [[BB2:BB[0-9]_[0-9]+]]-([[LONGBB0]]+4)
334 ; GCN-NEXT: s_add_u32 vcc_lo, vcc_lo, [[BB3:BB[0-9]+_[0-9]+]]-([[LONGBB1]]+4)
393 ; GCN-NEXT: s_add_u32 vcc_lo, vcc_lo, [[BB2:BB[0-9]_[0-9]+]]-([[LONGBB]]+4)
497 ; GCN: s_add_u32 vcc_lo, vcc_lo, [[LONG_BR_DEST0:BB[0-9]+_[0-9]+]]-(
Dnested-calls.ll15 ; GCN-DAG: s_add_u32 s32, s32, 0x400
36 ; GCN: s_add_u32 s32, s32, 0x1400{{$}}
Dllvm.amdgcn.implicitarg.ptr.ll123 ; HSA: s_add_u32 s6, s4, 0x70
124 ; MESA: s_add_u32 s6, s4, 0x70
138 ; GCN: s_add_u32 s6, s4, 0x70
221 ; GCN: s_add_u32 s8, s6, 0x70
Dbyval-frame-setup.ll37 ; GCN-DAG: s_add_u32 s32, s32, 0xc00{{$}}
72 ; GCN-DAG: s_add_u32 s32, s32, 0xc00{{$}}
86 ; GCN-NOT: s_add_u32 s32, s32, 0x800
133 ; GCN: s_add_u32 s32, s33, 0xc00{{$}}
140 ; GCN-NOT: s_add_u32 s32, s32, 0x800
/external/llvm/test/CodeGen/AMDGPU/
Dglobal-variable-relocs.ll17 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], private+8
31 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], internal+8
45 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], available_externally@GOTPCREL+4
48 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
62 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce@GOTPCREL+4
65 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
79 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak@GOTPCREL+4
82 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
96 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], common@GOTPCREL+4
99 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
[all …]
Dglobal-constant.ll9 ; GCN-NEXT: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], readonly
12 ; GCN-NEXT: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], readonly
/external/llvm/test/MC/AMDGPU/
Dtrap.s9 s_add_u32 ttmp0, ttmp0, 4 label
13 s_add_u32 ttmp4, 8, ttmp4 label
17 s_add_u32 ttmp4, ttmp4, 0x00000100 label
21 s_add_u32 ttmp4, ttmp4, 4 label
25 s_add_u32 ttmp4, ttmp8, ttmp4 label
Dsop2.s7 s_add_u32 s1, s2, s3 label
167 s_add_u32 s101, s102, s103 label
Dexpressions.s28 s_add_u32 s0, s0, global+4 label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dtrap_gfx9.txt7 # GFX9: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x6c,0x84,0x6c,0x80]
10 # GFX9: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x70,0x70,0x80]
13 # GFX9: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
16 # GFX9: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x70,0x84,0x70,0x80]
19 # GFX9: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x74,0x70,0x70,0x80]
64 # GFX9: s_add_u32 ttmp0, ttmp12, 4 ; encoding: [0x78,0x84,0x6c,0x80]
67 # GFX9: s_add_u32 ttmp0, ttmp13, 4 ; encoding: [0x79,0x84,0x6c,0x80]
70 # GFX9: s_add_u32 ttmp0, ttmp14, 4 ; encoding: [0x7a,0x84,0x6c,0x80]
73 # GFX9: s_add_u32 ttmp0, ttmp15, 4 ; encoding: [0x7b,0x84,0x6c,0x80]
Dtrap_vi.txt7 # VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
10 # VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
13 # VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
16 # VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
19 # VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dtrap_vi.txt7 # VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
10 # VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
13 # VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
16 # VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
19 # VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]

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