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Searched refs:s_and_b64 (Results 1 – 25 of 62) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dscalar-branch-missing-and-exec.ll7 ; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
17 ; The check for "s_and_b64 vcc, exec, something" checks that the bug is fixed.
21 ; CHECK: s_and_b64 vcc, exec,
Dbranch-condition-and.ll7 ; s_and_b64 s[2:3], s[0:1], s[2:3] ; def & use of the same register pair
15 ; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]]
Dwqm.ll22 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
45 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
67 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
96 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
387 ;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]]
388 ;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]]
425 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
429 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
473 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
538 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
[all …]
Dinfinite-loop.ll36 ; SI: s_and_b64 vcc, exec, -1
76 ; SI: s_and_b64 vcc, exec, -1
85 ; SI: s_and_b64 vcc, exec, -1
Dselect-opt.ll10 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
26 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
42 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
58 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
Delse.ll32 ; CHECK-NEXT: s_and_b64 exec, exec, [[INIT_EXEC]]
33 ; CHECK-NEXT: s_and_b64 [[AND_INIT:s\[[0-9]+:[0-9]+\]]], exec, [[DST]]
Dand.ll172 ; SI: s_and_b64
205 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}
405 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
420 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
435 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
450 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
491 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
506 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
Dloop_exit_with_xor.ll10 ; GCN: s_and_b64 [[REG2:[^ ,]*]], exec, [[REG1]]
64 ; GCN: s_and_b64 [[REG2:[^ ,]*]], exec, [[REG1]]
Dcontrol-flow-fastregalloc.ll22 ; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO]]:[…
103 ; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO:[0-…
128 ; GCN: s_and_b64 vcc, exec, vcc
180 ; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO:[0-…
Dnested-loop-conditions.ll182 ; GCN: s_and_b64 vcc, exec, vcc
187 ; GCN-NEXT: s_and_b64 vcc, exec, vcc
193 ; GCN-NEXT: s_and_b64 vcc, exec, vcc
199 ; GCN-NEXT: s_and_b64 vcc, exec, vcc
Dmultilevel-break.ll34 ; GCN-NEXT: s_and_b64 [[MASKED_SAVE_BREAK:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_BREAK]]
44 ; GCN-NEXT: s_and_b64 [[MASKED2_SAVE_BREAK:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_BREAK]]
Dsi-annotate-cf.ll93 ; SI: s_and_b64 vcc, exec, [[CMP4]]
102 ; SI-NEXT: s_and_b64 vcc, exec,
Dand-gcn.ll5 ; SI: s_and_b64
Dpartially-dead-super-register-immediate.ll4 ; s_and_b64. This is split into 2 x v_and_i32, part of the immediate
Dllvm.amdgcn.kill.ll54 ; SI: s_and_b64 exec, exec, s[0:1]
229 ; SI: s_and_b64 exec, exec, s[0:1]
256 ; SI: s_and_b64 exec
Dllvm.amdgcn.wqm.vote.ll36 ;FIXME: This could just be: s_and_b64 exec, exec, [[WQM]]
Dcontrol-flow-optnone.ll14 ; GCN: s_and_b64
/external/llvm/test/CodeGen/AMDGPU/
Dwqm.ll40 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
62 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
122 ;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]]
123 ;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]]
158 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
162 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
208 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
284 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
323 ; CHECK: s_and_b64 exec, exec, [[ORIG]]
346 ; CHECK: s_and_b64 exec, exec, [[ORIG]]
Dsmrd-vccz-bug.ll8 ; GCN: s_and_b64 vcc, exec, [[MASK]]
32 ; GCN: s_and_b64 vcc, exec, vcc
Duniform-cfg.ll35 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
92 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
123 ; SI: s_and_b64 vcc, exec, [[COND]]
148 ; SI: s_and_b64 vcc, exec, [[COND]]
257 ; SI: s_and_b64 vcc, exec, [[MASK]]
288 ; SI: s_and_b64 vcc, exec, vcc
Dand.ll164 ; SI: s_and_b64
193 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}
369 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
384 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
399 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
414 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
455 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
470 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
Di1-copy-implicit-def.ll7 ; SI-NEXT: s_and_b64 vcc, exec
Dpartially-dead-super-register-immediate.ll4 ; s_and_b64. This is split into 2 x v_and_i32, part of the immediate
Duniform-loop-inside-nonuniform.ll10 ; CHECK: s_and_b64 vcc, exec, vcc
/external/llvm/test/MC/AMDGPU/
Dsop2.s47 s_and_b64 s[2:3], s[4:5], s[6:7] label

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