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Searched refs:s_ashr_i32 (Results 1 – 25 of 30) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dload-constant-i32.ll93 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[SLO]], 31
120 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[LO]], 31
142 ; GCN-DAG: s_ashr_i32
143 ; GCN-DAG: s_ashr_i32
168 ; GCN: s_ashr_i32
169 ; GCN: s_ashr_i32
170 ; GCN: s_ashr_i32
171 ; GCN: s_ashr_i32
204 ; GCN: s_ashr_i32
205 ; GCN: s_ashr_i32
[all …]
Dsign_extend.ll15 ; GCN: s_ashr_i32
39 ; GCN: s_ashr_i32
108 ; GCN-DAG: s_ashr_i32 [[EXT3:s[0-9]+]], [[VAL]], 24
184 ; SI-DAG: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
186 ; VI: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
187 ; VI: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
Dashr.v2i16.ll15 ; CIVI-DAG: s_ashr_i32
16 ; CIVI-DAG: s_ashr_i32
19 ; CIVI-DAG: s_ashr_i32
20 ; CIVI-DAG: s_ashr_i32
Dload-constant-i16.ll164 ; GCN-DAG: s_ashr_i32
253 ; GCN-DAG: s_ashr_i32
312 ; GCN-DAG: s_ashr_i32
361 ; GCN-DAG: s_ashr_i32
393 ; GCN-DAG: s_ashr_i32
Dsra.ll235 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
262 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
Dbfe-patterns.ll144 ; GCN: s_ashr_i32 s{{[0-9]+}}, [[SHL]], [[SUB]]
Dmin.ll111 ; SI: s_ashr_i32
113 ; SI: s_ashr_i32
Dload-constant-i8.ll227 ; GCN-DAG: s_ashr_i32
276 ; GCN-DAG: s_ashr_i32
Dsext-in-reg.ll139 ; XGCN: s_ashr_i32 {{v[0-9]+}}, [[EXTRACT]], 31
/external/llvm/test/CodeGen/AMDGPU/
Dload-constant-i32.ll93 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[SLO]], 31
120 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[LO]], 31
142 ; GCN-DAG: s_ashr_i32
143 ; GCN-DAG: s_ashr_i32
168 ; GCN: s_ashr_i32
169 ; GCN: s_ashr_i32
170 ; GCN: s_ashr_i32
171 ; GCN: s_ashr_i32
204 ; GCN: s_ashr_i32
205 ; GCN: s_ashr_i32
[all …]
Dsign_extend.ll15 ; GCN: s_ashr_i32
39 ; GCN: s_ashr_i32
70 ; GCN-DAG: s_ashr_i32 [[EXT3:s[0-9]+]], [[VAL]], 24
126 ; GCN-DAG: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
Dload-constant-i16.ll140 ; GCN-DAG: s_ashr_i32
194 ; GCN-DAG: s_ashr_i32
229 ; GCN-DAG: s_ashr_i32
251 ; GCN-DAG: s_ashr_i32
274 ; GCN-DAG: s_ashr_i32
Dsra.ll205 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
232 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
Dload-constant-i8.ll197 ; GCN-DAG: s_ashr_i32
231 ; GCN-DAG: s_ashr_i32
Dsext-in-reg.ll138 ; XSI: s_ashr_i32 {{v[0-9]+}}, [[EXTRACT]], 31
/external/llvm/test/MC/AMDGPU/
Dsop2.s123 s_ashr_i32 s2, s4, s6 label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsop2.s129 s_ashr_i32 s2, s4, s6 label
Dgfx7_asm_all.s18777 s_ashr_i32 s5, s1, s2 label
18780 s_ashr_i32 s103, s1, s2 label
18783 s_ashr_i32 flat_scratch_lo, s1, s2 label
18786 s_ashr_i32 flat_scratch_hi, s1, s2 label
18789 s_ashr_i32 vcc_lo, s1, s2 label
18792 s_ashr_i32 vcc_hi, s1, s2 label
18795 s_ashr_i32 tba_lo, s1, s2 label
18798 s_ashr_i32 tba_hi, s1, s2 label
18801 s_ashr_i32 tma_lo, s1, s2 label
18804 s_ashr_i32 tma_hi, s1, s2 label
[all …]
Dgfx8_asm_all.s19449 s_ashr_i32 s5, s1, s2 label
19452 s_ashr_i32 s101, s1, s2 label
19455 s_ashr_i32 flat_scratch_lo, s1, s2 label
19458 s_ashr_i32 flat_scratch_hi, s1, s2 label
19461 s_ashr_i32 vcc_lo, s1, s2 label
19464 s_ashr_i32 vcc_hi, s1, s2 label
19467 s_ashr_i32 tba_lo, s1, s2 label
19470 s_ashr_i32 tba_hi, s1, s2 label
19473 s_ashr_i32 tma_lo, s1, s2 label
19476 s_ashr_i32 tma_hi, s1, s2 label
[all …]
Dgfx9_asm_all.s17494 s_ashr_i32 s5, s1, s2 label
17497 s_ashr_i32 s101, s1, s2 label
17500 s_ashr_i32 flat_scratch_lo, s1, s2 label
17503 s_ashr_i32 flat_scratch_hi, s1, s2 label
17506 s_ashr_i32 vcc_lo, s1, s2 label
17509 s_ashr_i32 vcc_hi, s1, s2 label
17512 s_ashr_i32 m0, s1, s2 label
17515 s_ashr_i32 exec_lo, s1, s2 label
17518 s_ashr_i32 exec_hi, s1, s2 label
17521 s_ashr_i32 s5, s101, s2 label
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt63 # VI: s_ashr_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x90]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt63 # VI: s_ashr_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x90]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td446 def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUAsmGFX7.rst432 s_ashr_i32 dst, src0, src1
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td290 defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32",

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