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Searched refs:s_dcache_inv (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.dcache.inv.ll9 ; SI-NEXT: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
10 ; VI-NEXT: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
19 ; GCN: s_dcache_inv
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.dcache.inv.ll9 ; SI-NEXT: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
10 ; VI-NEXT: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
19 ; GCN: s_dcache_inv
/external/llvm/test/MC/AMDGPU/
Dsmrd.s147 s_dcache_inv label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsmrd.s218 s_dcache_inv label
Dgfx7_asm_all.s10431 s_dcache_inv label
Dgfx8_asm_all.s10989 s_dcache_inv label
Dgfx9_asm_all.s11461 s_dcache_inv label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dsmrd_vi.txt72 # VI: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
Dgfx8_dasm_all.txt7725 # CHECK: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
Dgfx9_dasm_all.txt9090 # CHECK: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsmrd_vi.txt69 # VI: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSMInstructions.td287 def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>;
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUAsmGFX7.rst355 s_dcache_inv
DAMDGPUAsmGFX8.rst366 s_dcache_inv
DAMDGPUUsage.rst2578 frame at the same address, respectively. There is no need for a ``s_dcache_inv``
DAMDGPUAsmGFX9.rst498 s_dcache_inv
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td83 defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",