Home
last modified time | relevance | path

Searched refs:s_load_dwordx8 (Results 1 – 25 of 37) sorted by relevance

12

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s40 s_load_dwordx8 s[104:111], s[2:3], s4 label
43 s_load_dwordx8 s[100:107], s[2:3], s4 label
46 s_load_dwordx8 s[108:115], s[2:3], s4 label
Dtrap.s209 s_load_dwordx8 ttmp[0:7], s[0:1], s0 label
213 s_load_dwordx8 ttmp[4:11], s[0:1], s0 label
217 s_load_dwordx8 ttmp[8:15], s[0:1], s0 label
Dsmrd.s110 s_load_dwordx8 s[8:15], s[2:3], 1 label
114 s_load_dwordx8 s[8:15], s[2:3], s4 label
118 s_load_dwordx8 s[96:103], s[2:3], s4 label
Dsmrd-err.s9 s_load_dwordx8 s[96:103], s[2:3], s4 label
Dsym_kernel_scope.s33 s_load_dwordx8 s[16:23], s[0:1], 0x0
/external/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s40 s_load_dwordx8 s[104:111], s[2:3], s4 label
43 s_load_dwordx8 s[100:107], s[2:3], s4 label
46 s_load_dwordx8 s[108:115], s[2:3], s4 label
Dsmrd.s63 s_load_dwordx8 s[8:15], s[2:3], 1 label
67 s_load_dwordx8 s[8:15], s[2:3], s4 label
71 s_load_dwordx8 s[96:103], s[2:3], s4 label
Dsmrd-err.s9 s_load_dwordx8 s[96:103], s[2:3], s4 label
/external/llvm/test/CodeGen/AMDGPU/
Dinline-constraints.ll11 ; GCN: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
21 …%s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
Dload-constant-i64.ll28 ; GCN: s_load_dwordx8 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
40 ; GCN: s_load_dwordx8
Dload-constant-i32.ll51 ; GCN: s_load_dwordx8
183 ; GCN: s_load_dwordx8
202 ; GCN: s_load_dwordx8
Dsi-scheduler.ll13 ; CHECK: s_load_dwordx8
Dkernel-args.ll297 ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
298 ; VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44
314 ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
Dload-constant-i16.ll64 ; GCN: s_load_dwordx8
239 ; GCN: s_load_dwordx8
250 ; GCN: s_load_dwordx8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dconstant-address-space-32bit.ll61 ; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
62 ; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x10
63 ; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
64 ; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
143 ; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
144 ; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x10
145 ; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
146 ; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
207 ; GCN: s_load_dwordx8
241 ; GCN: s_load_dwordx8
Dload-constant-i64.ll28 ; GCN: s_load_dwordx8 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
40 ; GCN: s_load_dwordx8
Dinline-constraints.ll15 ; GCN: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
29 …%s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
Dkernel-args.ll445 ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
446 ; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44
447 ; HSA-VI: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x20
465 ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
531 ; SI: s_load_dwordx8 s
536 ; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44
538 ; HSA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20
Dload-constant-f32.ll6 ; GCN: s_load_dwordx8
Dload-constant-i32.ll51 ; GCN: s_load_dwordx8
183 ; GCN: s_load_dwordx8
202 ; GCN: s_load_dwordx8
Dsi-scheduler.ll13 ; CHECK: s_load_dwordx8
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dtrap_gfx9.txt124 # GFX9: s_load_dwordx8 ttmp[0:7], s[0:1], s0 ; encoding: [0x00,0x1b,0x0c,0xc0,0x00,0x00,0x00,0x00]
127 # GFX9: s_load_dwordx8 ttmp[4:11], s[0:1], s0 ; encoding: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x0…
130 # GFX9: s_load_dwordx8 ttmp[8:15], s[0:1], s0 ; encoding: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x0…
Dsmrd_vi.txt30 # VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
33 # VI: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]
Dtrap_vi.txt121 # VI: s_load_dwordx8 ttmp[0:7], s[0:1], s0 ; encoding: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00]
124 # VI: s_load_dwordx8 ttmp[4:11], s[0:1], s0 ; encoding: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsmrd_vi.txt27 # VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
30 # VI: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]

12