/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | widen-smrd-loads.ll | 7 ; GCN: s_or_b32 [[OR:s[0-9]+]], [[VAL]], 4 20 ; GCN: s_or_b32 [[OR:s[0-9]+]], [[TRUNC]], 4 34 ; GCN: s_or_b32 [[OR:s[0-9]+]], [[EXT]], 4 47 ; GCN: s_or_b32 [[OR:s[0-9]+]], [[ADD]], 4 75 ; SI: s_or_b32 78 ; SI: s_or_b32 79 ; SI: s_or_b32 120 ; GCN: s_or_b32 [[OR:s[0-9]+]], [[TRUNC]], 4 146 ; GCN: s_or_b32 [[OR:s[0-9]+]], [[VAL]], 4 158 ; GCN: s_or_b32 [[OR:s[0-9]+]], [[VAL]], 1
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D | fneg-fabs.f16.ll | 43 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000 53 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000 91 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008000 101 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]] 102 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]] 113 ; CI: s_or_b32 [[FNEG_FABS:s[0-9]+]], [[IN]], 0x80008000
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D | or.ll | 41 ; SI: s_or_b32 58 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f 67 ; SI-DAG: s_or_b32 s[[RES_HI:[0-9]+]], s[[HI]], 0xf237b 68 ; SI-DAG: s_or_b32 s[[RES_LO:[0-9]+]], s[[LO]], 0x3039 97 ; SI: s_or_b32 s[[VAL_LO]], s[[VAL_LO]], 63 112 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 63 124 ; SI-DAG: s_or_b32 [[VAL]], [[VAL]], -8 239 ; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]]
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D | fneg-fabs.ll | 37 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 51 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 61 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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D | insert_vector_elt.v2i16.ll | 9 ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], 0x3e7{{$}} 26 ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]] 45 ; CI-DAG: s_or_b32 s{{[0-9]+}}, [[ELT0_MASKED]], [[ELT1]] 52 ; VI-DAG: s_or_b32 [[OR:s[0-9]+]], [[ELT_MASKED]], [[VEC_HIMASK]] 77 ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT_HI]], [[ELT1]] 97 ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], [[ELT0]] 120 ; CI: s_or_b32 s{{[0-9]+}}, [[ELT_HI]], [[VEC_HI]] 126 ; VI: s_or_b32 s{{[0-9]+}}, [[ELT_HI]], [[MASK_HI]] 154 ; CIVI: s_or_b32 [[INS:s[0-9]+]], [[ELT0]], 0x3e70000 170 ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]] [all …]
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D | shl.v2i16.ll | 21 ; VI: s_or_b32 32 ; CI: s_or_b32
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D | gep-address-space.ll | 17 ; SI: s_or_b32
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D | indirect-addressing-si.ll | 33 ; GCN-DAG: s_or_b32 34 ; GCN-DAG: s_or_b32 35 ; GCN-DAG: s_or_b32 36 ; GCN-DAG: s_or_b32
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D | partial-shift-shrink.ll | 93 ; GCN: s_or_b32 [[RESULT:s[0-9]+]], [[VAL_SHIFT]], 4
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D | local-64.ll | 51 ; SI-DAG: s_or_b32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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D | ashr.v2i16.ll | 23 ; CIVI: s_or_b32
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/external/llvm/test/CodeGen/AMDGPU/ |
D | fneg-fabs.ll | 37 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 51 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 61 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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D | or.ll | 41 ; SI: s_or_b32 58 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f 145 ; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]]
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D | indirect-addressing-si.ll | 24 ; CHECK-DAG: s_or_b32 25 ; CHECK-DAG: s_or_b32 26 ; CHECK-DAG: s_or_b32 27 ; CHECK-DAG: s_or_b32
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D | gep-address-space.ll | 17 ; SI: s_or_b32
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D | local-64.ll | 38 ; SI: s_or_b32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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/external/llvm/test/MC/AMDGPU/ |
D | trap.s | 93 s_or_b32 ttmp9, ttmp9, 0x00280000 label
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D | sop2.s | 51 s_or_b32 s2, s4, s6 label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
D | trap.s | 120 s_or_b32 ttmp9, ttmp9, 0x00280000 label
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D | sop2.s | 57 s_or_b32 s2, s4, s6 label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
D | sop2_vi.txt | 9 # VI: s_or_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x87]
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D | trap_vi.txt | 70 # VI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00]
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D | trap_gfx9.txt | 61 # GFX9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
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/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | sop2_vi.txt | 9 # VI: s_or_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x87]
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D | trap_vi.txt | 70 # VI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00]
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