| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | expressions.s | 49 s_sub_u32 vcc_lo, vcc_lo, (BB2+4)-BB1 label
54 s_sub_u32 s0, s0, -t label
58 s_sub_u32 s0, s0, -t label
|
| D | sop2.s | 16 s_sub_u32 s1, s2, s3 label
|
| D | gfx7_asm_all.s | 14406 s_sub_u32 s5, s1, s2 label
14409 s_sub_u32 s103, s1, s2 label
14412 s_sub_u32 flat_scratch_lo, s1, s2 label
14415 s_sub_u32 flat_scratch_hi, s1, s2 label
14418 s_sub_u32 vcc_lo, s1, s2 label
14421 s_sub_u32 vcc_hi, s1, s2 label
14424 s_sub_u32 tba_lo, s1, s2 label
14427 s_sub_u32 tba_hi, s1, s2 label
14430 s_sub_u32 tma_lo, s1, s2 label
14433 s_sub_u32 tma_hi, s1, s2 label
[all …]
|
| D | gfx8_asm_all.s | 15078 s_sub_u32 s5, s1, s2 label
15081 s_sub_u32 s101, s1, s2 label
15084 s_sub_u32 flat_scratch_lo, s1, s2 label
15087 s_sub_u32 flat_scratch_hi, s1, s2 label
15090 s_sub_u32 vcc_lo, s1, s2 label
15093 s_sub_u32 vcc_hi, s1, s2 label
15096 s_sub_u32 tba_lo, s1, s2 label
15099 s_sub_u32 tba_hi, s1, s2 label
15102 s_sub_u32 tma_lo, s1, s2 label
15105 s_sub_u32 tma_hi, s1, s2 label
[all …]
|
| D | gfx9_asm_all.s | 14332 s_sub_u32 s5, s1, s2 label
14335 s_sub_u32 s101, s1, s2 label
14338 s_sub_u32 flat_scratch_lo, s1, s2 label
14341 s_sub_u32 flat_scratch_hi, s1, s2 label
14344 s_sub_u32 vcc_lo, s1, s2 label
14347 s_sub_u32 vcc_hi, s1, s2 label
14350 s_sub_u32 m0, s1, s2 label
14353 s_sub_u32 exec_lo, s1, s2 label
14356 s_sub_u32 exec_hi, s1, s2 label
14359 s_sub_u32 s5, s101, s2 label
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | frame-index-elimination.ll | 10 ; GCN: s_sub_u32 s6, s5, s4
31 ; GCN: s_sub_u32 s6, s5, s4
55 ; GCN: s_sub_u32 s6, s5, s4
93 ; GCN-NEXT: s_sub_u32 [[SUB_OFFSET:s[0-9]+]], s5, s4
132 ; GCN: s_sub_u32 [[SUB_OFFSET:s[0-9]+]], s5, s4
166 ; GCN: s_sub_u32 s6, s5, s4
190 ; GCN: s_sub_u32 [[DIFF:s[0-9]+]], s5, s4
|
| D | stack-realign.ll | 42 ; GCN: s_sub_u32 s32, s32, 0x2800
63 ; GCN: s_sub_u32 s32, s32, 0x3000
79 ; GCN: s_sub_u32 s32, s32, 0xd00
|
| D | nested-calls.ll | 26 ; GCN: s_sub_u32 s32, s32, 0x400
39 ; GCN: s_sub_u32 s32, s32, 0x1400{{$}}
|
| D | spill-offset-calculation.ll | 40 ; CHECK: s_sub_u32 s7, s7, 0x40000
94 ; CHECK: s_sub_u32 s7, s7, 0x3ff00
144 ; CHECK: s_sub_u32 s5, s5, 0x40000
198 ; CHECK: s_sub_u32 s5, s5, 0x3ff00
|
| D | byval-frame-setup.ll | 53 ; GCN: s_sub_u32 s32, s32, 0xc00{{$}}
108 ; GCN-NOT: s_sub_u32 s32, s32, 0x800
110 ; GCN: s_sub_u32 s32, s32, 0xc00{{$}}
164 ; GCN-NOT: s_sub_u32 s32
|
| D | usubo.ll | 7 ; GCN: s_sub_u32
93 ; GCN: s_sub_u32
|
| D | branch-relaxation.ll | 195 ; GCN-NEXT: s_sub_u32 vcc_lo, vcc_lo, ([[LONG_JUMP]]+4)-[[LOOPBB]]
293 ; GCN-NEXT: s_sub_u32 vcc_lo, vcc_lo, ([[LONGBB]]+4)-[[LOOP]]
458 ; GCN-NEXT: s_sub_u32 vcc_lo, vcc_lo, ([[LONGBB]]+4)-[[LOOP_BODY]]
|
| D | ssubo.ll | 43 ; GCN: s_sub_u32
|
| D | callee-frame-setup.ll | 85 ; GCN: s_sub_u32 s32, s32, 0x400
|
| D | sub.ll | 145 ; GCN: s_sub_u32
|
| D | sibling-call.ll | 233 ; GCN: s_sub_u32 s32, s32, 0x400
|
| D | call-argument-types.ll | 677 ; GCN-NOT: s_sub_u32 [[SP]]
|
| D | callee-special-input-vgprs.ll | 338 ; GCN: s_sub_u32 s32, s32, 0x400{{$}}
|
| /external/llvm/test/MC/AMDGPU/ |
| D | sop2.s | 10 s_sub_u32 s1, s2, s3 label
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | ssubo.ll | 42 ; SI: s_sub_u32
|
| D | usubo.ll | 53 ; SI: s_sub_u32
|
| D | sub.ll | 58 ; SI: s_sub_u32
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SOPInstructions.td | 347 def S_SUB_U32 : SOP2_32 <"s_sub_u32">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUAsmGFX7.rst | 461 s_sub_u32 dst, src0, src1
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 203 defm S_SUB_U32 : SOP2_32 <sop2<0x01>, "s_sub_u32", []>;
|