| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | scalar-branch-missing-and-exec.ll | 7 ; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
10 ; The problematic case is s_xor_b64, as, unlike the other ops, it can actually
13 ; The check for an s_xor_b64 is just to check that this test tests what it is
14 ; supposed to test. If the s_xor_b64 disappears due to some other case, it does
20 ; CHECK: s_xor_b64
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| D | si-lower-control-flow-kill.ll | 5 ; GCN-NEXT: s_xor_b64 s[{{[0-9:]+}}], exec, [[SAVEEXEC]]
21 ; GCN-NEXT: s_xor_b64 s[{{[0-9:]+}}], exec, [[SAVEEXEC]]
47 ; GCN-NEXT: s_xor_b64 s[{{[0-9:]+}}], exec, [[SAVEEXEC]]
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| D | valu-i1.ll | 13 ; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]]
27 ; SI-NEXT: s_xor_b64 exec, exec, [[SAVE3]]
122 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
130 ; SI-NEXT: s_xor_b64 exec, exec
215 ; SI: s_xor_b64 [[ORNEG3:s\[[0-9]+:[0-9]+\]]], exec, [[ORNEG2]]
|
| D | xor.ll | 45 ; SI: s_xor_b64 [[XOR:vcc]], [[CMP1]], [[CMP0]]
123 ; SI: s_xor_b64
155 ; SI: s_xor_b64
191 ; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
222 ; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -8
|
| D | else.ll | 7 ; CHECK-NEXT: s_xor_b64 exec, exec, [[DST]]
34 ; CHECK-NEXT: s_xor_b64 exec, exec, [[AND_INIT]]
|
| D | loop_exit_with_xor.ll | 9 ; GCN: s_xor_b64 [[REG1:[^ ,]*]], {{[^ ,]*, -1$}}
63 ; GCN: s_xor_b64 [[REG1:[^ ,]*]], {{[^ ,]*, -1$}}
|
| D | collapse-endcf.ll | 81 ; GCN-NEXT: s_xor_b64 [[SAVEEXEC_INNER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_INNER]]
87 ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_INNER3]]
122 ; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]]
135 ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_OUTER3]]
|
| D | si-annotate-cfg-loop-assert.ll | 5 ; CHECK s_xor_b64
|
| D | trunc-cmp-constant.ll | 25 ; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1
122 ; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1
|
| D | llvm.amdgcn.ps.live.ll | 37 ; CHECK-DAG: s_xor_b64 [[HELPER:s\[[0-9]+:[0-9]+\]]], [[LIVE]], -1
|
| D | xnor.ll | 47 ; GCN: s_xor_b64
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | i1-copy-phi.ll | 7 ; SI: s_xor_b64
11 ; SI: s_xor_b64
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| D | si-lower-control-flow-unreachable-block.ll | 6 ; GCN: s_xor_b64
31 ; GCN: s_xor_b64
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| D | valu-i1.ll | 48 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
74 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
117 ; SI: s_xor_b64 [[OUTER_CMP_SREG]], exec, [[OUTER_CMP_SREG]]
133 ; SI: s_xor_b64 [[ORNEG2]], exec, [[ORNEG2]]
|
| D | xor.ll | 45 ; SI: s_xor_b64 [[XOR:vcc]], [[CMP0]], [[CMP1]]
123 ; SI: s_xor_b64
155 ; SI: s_xor_b64
|
| D | si-annotate-cfg-loop-assert.ll | 5 ; CHECK s_xor_b64
|
| D | subreg-coalescer-undef-use.ll | 13 ; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
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| D | uniform-loop-inside-nonuniform.ll | 35 ;CHECK: s_xor_b64
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| D | trunc-cmp-constant.ll | 23 ; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1
120 ; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1
|
| D | llvm.amdgcn.ps.live.ll | 35 ; CHECK-DAG: s_xor_b64 [[HELPER:s\[[0-9]+:[0-9]+\]]], [[LIVE]], -1
|
| D | uniform-cfg.ll | 310 ; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
340 ; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
367 ; SI: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
|
| D | indirect-addressing-si.ll | 218 ; CHECK-NEXT: s_xor_b64 exec, exec, vcc
231 ; CHECK-NEXT: s_xor_b64 exec, exec, vcc
274 ; CHECK-NEXT: s_xor_b64 exec, exec, vcc
288 ; CHECK-NEXT: s_xor_b64 exec, exec, vcc
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| D | ret_jump.ll | 11 ; GCN-NEXT: s_xor_b64 [[XOR_EXEC:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_EXEC]]
|
| /external/llvm/test/MC/AMDGPU/ |
| D | sop2.s | 63 s_xor_b64 s[2:3], s[4:5], s[6:7] label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | sop2.s | 69 s_xor_b64 s[2:3], s[4:5], s[6:7] label
|