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Searched refs:sbfiz (Results 1 – 25 of 31) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-bitfield-encoding.s14 sbfiz wzr, w0, #31, #1
15 sbfiz xzr, x0, #31, #1
25 ; CHECK: sbfiz wzr, w0, #31, #1 ; encoding: [0x1f,0x00,0x01,0x13]
26 ; CHECK: sbfiz xzr, x0, #31, #1 ; encoding: [0x1f,0x00,0x61,0x93]
Dbasic-a64-diagnostics.s892 sbfiz w1, w2, #0, #0
893 sbfiz wsp, w9, #0, #1
894 sbfiz w9, w10, #32, #1
895 sbfiz w11, w12, #32, #0
896 sbfiz w9, w10, #10, #23
897 sbfiz x3, x5, #12, #53
898 sbfiz sp, x3, #7, #6
899 sbfiz w3, wsp, #10, #8
Dbasic-a64-instructions.s1031 sbfiz w9, w10, #0, #1
1032 sbfiz x2, x3, #63, #1
1033 sbfiz x19, x20, #0, #64
1034 sbfiz x9, x10, #5, #59
1035 sbfiz w9, w10, #0, #32
1036 sbfiz w11, w12, #31, #1
1037 sbfiz w13, w14, #29, #3
1038 sbfiz xzr, xzr, #10, #11
/external/llvm/test/MC/AArch64/
Darm64-bitfield-encoding.s14 sbfiz wzr, w0, #31, #1
15 sbfiz xzr, x0, #31, #1
25 ; CHECK: sbfiz wzr, w0, #31, #1 ; encoding: [0x1f,0x00,0x01,0x13]
26 ; CHECK: sbfiz xzr, x0, #31, #1 ; encoding: [0x1f,0x00,0x61,0x93]
Dbasic-a64-diagnostics.s887 sbfiz w1, w2, #0, #0
888 sbfiz wsp, w9, #0, #1
889 sbfiz w9, w10, #32, #1
890 sbfiz w11, w12, #32, #0
891 sbfiz w9, w10, #10, #23
892 sbfiz x3, x5, #12, #53
893 sbfiz sp, x3, #7, #6
894 sbfiz w3, wsp, #10, #8
Dbasic-a64-instructions.s1031 sbfiz w9, w10, #0, #1
1032 sbfiz x2, x3, #63, #1
1033 sbfiz x19, x20, #0, #64
1034 sbfiz x9, x10, #5, #59
1035 sbfiz w9, w10, #0, #32
1036 sbfiz w11, w12, #31, #1
1037 sbfiz w13, w14, #29, #3
1038 sbfiz xzr, xzr, #10, #11
/external/llvm/test/CodeGen/AArch64/
Darm64-shifted-sext.ll9 ; CHECK: sbfiz w0, [[REG]], #4, #8
33 ; CHECK: sbfiz w0, [[REG]], #8, #8
58 ; CHECK: sbfiz w0, [[REG]], #4, #8
80 ; CHECK: sbfiz w0, [[REG]], #8, #8
103 ; CHECK: sbfiz x0, x[[REG]], #4, #8
125 ; CHECK: sbfiz x0, x[[REG]], #8, #8
148 ; CHECK: sbfiz w0, [[REG]], #4, #16
193 ; CHECK: sbfiz x0, x[[REG]], #4, #16
215 ; CHECK: sbfiz x0, x[[REG]], #16, #16
238 ; CHECK: sbfiz x0, x[[REG]], #4, #32
Dfast-isel-shift.ll104 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
120 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
136 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
168 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
184 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
200 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
232 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
248 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
278 ; CHECK: sbfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
Dxbfiz.ll5 ; CHECK: sbfiz x0, x0, #1, #16
13 ; CHECK: sbfiz w0, w0, #1, #14
Dfast-isel-addressing-modes.ll568 ; CHECK: sbfiz [[REG:x[0-9]+]], {{x[0-9]+}}, #3, #32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-shifted-sext.ll9 ; CHECK: sbfiz w0, [[REG]], #4, #8
33 ; CHECK: sbfiz w0, [[REG]], #8, #8
58 ; CHECK: sbfiz w0, [[REG]], #4, #8
80 ; CHECK: sbfiz w0, [[REG]], #8, #8
103 ; CHECK: sbfiz x0, x[[REG]], #4, #8
125 ; CHECK: sbfiz x0, x[[REG]], #8, #8
148 ; CHECK: sbfiz w0, [[REG]], #4, #16
193 ; CHECK: sbfiz x0, x[[REG]], #4, #16
215 ; CHECK: sbfiz x0, x[[REG]], #16, #16
238 ; CHECK: sbfiz x0, x[[REG]], #4, #32
Dfast-isel-shift.ll104 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
120 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
136 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
168 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
184 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
200 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
232 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
248 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
278 ; CHECK: sbfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
Dxbfiz.ll5 ; CHECK: sbfiz x0, x0, #1, #16
13 ; CHECK: sbfiz w0, w0, #1, #14
Dfast-isel-addressing-modes.ll568 ; CHECK: sbfiz [[REG:x[0-9]+]], {{x[0-9]+}}, #3, #32
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs421 0x49,0x01,0x00,0x13 = sbfiz w9, w10, #0, #1
422 0x62,0x00,0x41,0x93 = sbfiz x2, x3, #63, #1
423 0x93,0xfe,0x40,0x93 = sbfiz x19, x20, #0, #64
424 0x49,0xe9,0x7b,0x93 = sbfiz x9, x10, #5, #59
425 0x49,0x7d,0x00,0x13 = sbfiz w9, w10, #0, #32
426 0x8b,0x01,0x01,0x13 = sbfiz w11, w12, #31, #1
427 0xcd,0x09,0x03,0x13 = sbfiz w13, w14, #29, #3
428 0xff,0x2b,0x76,0x93 = sbfiz xzr, xzr, #10, #11
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h874 sbfiz(rd, rn, lsb, width); in Sbfiz()
Dassembler-arm64.h1395 void sbfiz(const Register& rd, const Register& rn, int lsb, int width) { in sbfiz() function
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt679 # CHECK: sbfiz x2, x3, #63, #1
681 # CHECK: sbfiz x9, x10, #5, #59
683 # CHECK: sbfiz w11, w12, #31, #1
684 # CHECK: sbfiz w13, w14, #29, #3
685 # CHECK: sbfiz xzr, xzr, #10, #11
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt680 # CHECK: sbfiz x2, x3, #63, #1
682 # CHECK: sbfiz x9, x10, #5, #59
684 # CHECK: sbfiz w11, w12, #31, #1
685 # CHECK: sbfiz w13, w14, #29, #3
686 # CHECK: sbfiz xzr, xzr, #10, #11
/external/vixl/src/aarch64/
Dassembler-aarch64.h779 void sbfiz(const Register& rd, in sbfiz() function
Dmacro-assembler-aarch64.h2144 sbfiz(rd, rn, lsb, width); in Sbfiz()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour229 0x~~~~~~~~~~~~~~~~ 131e0a30 sbfiz w16, w17, #2, #3
230 0x~~~~~~~~~~~~~~~~ 937c1272 sbfiz x18, x19, #4, #5
Dlog-disasm229 0x~~~~~~~~~~~~~~~~ 131e0a30 sbfiz w16, w17, #2, #3
230 0x~~~~~~~~~~~~~~~~ 937c1272 sbfiz x18, x19, #4, #5
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc282 __ sbfiz(w16, w17, 2, 3); in GenerateTestSequenceBase() local
283 __ sbfiz(x18, x19, 4, 5); in GenerateTestSequenceBase() local
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md994 void sbfiz(const Register& rd,

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