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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/AMDGPU/
Dtarget-index-operands.mir39 …gpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
40 …gpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
41 … $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
42 $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
44 $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
45 $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
46 $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
47 $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
48 $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
49 $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
[all …]
Dexpected-target-index-name.mir32 $sgpr2 = S_ADD_U32 $sgpr2, target-index(0), implicit-def $scc, implicit-def $scc
33 … $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
34 $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
36 $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
37 $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
38 $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
39 $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
40 $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
41 $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
Dinvalid-target-index-operand.mir32 $sgpr2 = S_ADD_U32 $sgpr2, target-index(constdata-start), implicit-def $scc, implicit-def $scc
33 … $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
34 $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
36 $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
37 $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
38 $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
39 $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
40 $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
41 $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
/external/llvm/test/CodeGen/MIR/AMDGPU/
Dtarget-index-operands.mir55 …gpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
56 …gpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
57 … %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
58 %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
60 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
61 %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
62 %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
63 %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
64 %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
65 %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
[all …]
Dinvalid-target-index-operand.mir47 %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc
48 … %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
49 %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
51 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
52 %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
53 %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
54 %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
55 %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
56 %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
Dexpected-target-index-name.mir47 %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc
48 … %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
49 %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
51 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
52 %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
53 %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
54 %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
55 %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
56 %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dendpgm-dce.mir19 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
22 %4 = S_ADD_U32 %3, 1, implicit-def $scc
27 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
43 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
46 %4 = S_ADD_U32 %3, 1, implicit-def $scc
51 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
67 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
70 %4 = S_ADD_U32 %3, 1, implicit-def $scc
75 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
88 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
[all …]
Dregcoal-subrange-join-seg.mir7 # GCN: S_CBRANCH_SCC1 %bb.6, implicit undef $scc
84 S_CBRANCH_SCC1 %bb.6, implicit undef $scc
88 S_CBRANCH_SCC1 %bb.4, implicit undef $scc
92 S_CBRANCH_SCC1 %bb.4, implicit undef $scc
100 S_CBRANCH_SCC1 %bb.6, implicit undef $scc
106 S_CBRANCH_SCC1 %bb.14, implicit undef $scc
110 S_CBRANCH_SCC1 %bb.9, implicit undef $scc
118 S_CBRANCH_SCC1 %bb.13, implicit undef $scc
122 S_CBRANCH_SCC1 %bb.12, implicit undef $scc
132 S_CBRANCH_SCC1 %bb.26, implicit undef $scc
[all …]
Doptimize-if-exec-masking.mir150 # CHECK: $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $e…
151 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
184 $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
185 $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
200 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
209 # CHECK: $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $e…
242 $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
257 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
266 # CHECK: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $ex…
299 $sgpr2_sgpr3 = S_OR_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
[all …]
Dcoalescer-subranges-another-prune-error.mir32 $exec = S_WQM_B64 $exec, implicit-def dead $scc
33 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
90 %44:sreg_64 = S_AND_B64 %43, %30, implicit-def dead $scc
91 %45:sreg_64 = S_XOR_B64 %44, %43, implicit-def dead $scc
98 $exec = S_OR_B64 $exec, %46, implicit-def $scc
104 %57:sreg_64 = S_AND_B64 $exec, %46, implicit-def $scc
105 %57:sreg_64 = S_OR_B64 %57, killed %55, implicit-def $scc
118 $exec = S_OR_B64 $exec, killed %60, implicit-def $scc
123 %68:sreg_64 = S_AND_B64 %67, %61, implicit-def dead $scc
147 $exec = S_OR_B64 $exec, %45, implicit-def $scc
[all …]
Dopt-sgpr-to-vgpr-copy.mir118 %15 = S_ADD_U32 killed %11, killed %13, implicit-def $scc
119 %16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead $scc, implicit $scc
126 … %1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
133 %24 = S_LSHL_B64 %0, killed %23, implicit-def dead $scc
143 SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
217 %16 = S_ADD_U32 %12, killed %14, implicit-def $scc
218 %17 = S_ADDC_U32 %13, killed %15, implicit-def dead $scc, implicit $scc
222 %21 = S_ADD_U32 %12, killed %19, implicit-def $scc
223 %22 = S_ADDC_U32 %13, killed %20, implicit-def dead $scc, implicit $scc
231 %31 = S_AND_B64 killed %27, killed %29, implicit-def dead $scc
[all …]
Dreduce-saveexec.mir12 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
25 $sgpr0_sgpr1 = S_AND_B64 killed $vcc, $exec, implicit-def $scc
38 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
52 $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
65 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
78 $sgpr0_sgpr1 = S_XOR_B64 $exec, killed $vcc, implicit-def $scc
91 $sgpr0_sgpr1 = S_ANDN2_B64 $exec, killed $vcc, implicit-def $scc
104 $sgpr0_sgpr1 = S_ORN2_B64 $exec, killed $vcc, implicit-def $scc
117 $sgpr0_sgpr1 = S_NAND_B64 $exec, killed $vcc, implicit-def $scc
130 $sgpr0_sgpr1 = S_NOR_B64 $exec, killed $vcc, implicit-def $scc
[all …]
Dmisched-killflags.mir15 BUNDLE implicit-def $sgpr6_sgpr7, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $scc {
17 $sgpr6 = S_ADD_U32 internal $sgpr6, 0, implicit-def $scc
18 $sgpr7 = S_ADDC_U32 internal $sgpr7,0, implicit-def $scc, implicit internal $scc
34 …CK: BUNDLE implicit-def $sgpr6_sgpr7, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $scc {
36 # CHECK: $sgpr6 = S_ADD_U32 internal $sgpr6, 0, implicit-def $scc
37 # CHECK: $sgpr7 = S_ADDC_U32 internal $sgpr7, 0, implicit-def $scc, implicit internal $scc
Dcoalescer-subregjoin-fullcopy.mir34 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
43 S_CBRANCH_SCC0 %bb.4, implicit undef $scc
78 %18:sreg_64 = S_AND_B64 killed %17, killed %14, implicit-def dead $scc
83 %23:sreg_64 = S_AND_B64 %22, %18, implicit-def dead $scc
84 %24:sreg_64 = S_XOR_B64 %23, %22, implicit-def dead $scc
91 $exec = S_OR_B64 $exec, %24, implicit-def $scc
95 %28:sreg_64 = S_OR_B64 %24, killed %27, implicit-def dead $scc
104 $exec = S_OR_B64 $exec, killed %28, implicit-def $scc
116 S_CBRANCH_SCC0 %bb.12, implicit undef $scc
125 S_CBRANCH_SCC1 %bb.13, implicit undef $scc
[all …]
Dcoalescer-with-subregs-bad-identical.mir30 S_CBRANCH_SCC1 %bb.21, implicit undef $scc
34 S_CBRANCH_SCC1 %bb.17, implicit undef $scc
58 S_CBRANCH_SCC0 %bb.4, implicit undef $scc
75 %24:sreg_64 = S_AND_B64 %23, %22, implicit-def dead $scc
89 %28:sreg_64 = S_AND_B64 $exec, killed %27, implicit-def dead $scc
97 $exec = S_OR_B64 $exec, killed %23, implicit-def $scc
106 S_CBRANCH_SCC1 %bb.11, implicit undef $scc
129 S_CBRANCH_SCC0 %bb.13, implicit undef $scc
154 %51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc
164 $exec = S_OR_B64 $exec, killed %50, implicit-def $scc
[all …]
Dsdwa-scalar-ops.mir220 %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc
221 %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc
232 %37 = S_ADD_U32 %14, 4, implicit-def $scc
233 %38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc
244 %55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc
245 %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc
248 S_CMPK_EQ_I32 %55, 4096, implicit-def $scc
249 S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc
383 %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc
384 %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc
[all …]
Dcoalescer-extend-pruned-subrange.mir21 %7:sreg_32_xm0 = S_AND_B32 target-flags(amdgpu-gotprel) 1, %2.sub0, implicit-def dead $scc
40 %21:sreg_64 = S_AND_B64 %20, %19, implicit-def dead $scc
56 $exec = S_OR_B64 $exec, %20, implicit-def $scc
60 S_CBRANCH_SCC0 %bb.7, implicit undef $scc
74 %30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc
93 $exec = S_OR_B64 $exec, %29, implicit-def $scc
110 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
Dsubreg-split-live-in-error.mir53 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
64 S_CBRANCH_SCC0 %bb.4, implicit undef $scc
79 S_CBRANCH_SCC1 %bb.22, implicit undef $scc
100 S_CBRANCH_SCC1 %bb.8, implicit undef $scc
113 S_CBRANCH_SCC0 %bb.10, implicit undef $scc
132 %17:sreg_64 = S_AND_B64 $exec, %16, implicit-def dead $scc
175 $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
188 %44:sreg_64 = S_AND_B64 %43, %43, implicit-def dead $scc
189 %45:sreg_64 = S_AND_B64 %42, %42, implicit-def dead $scc
190 %46:sreg_64 = S_AND_B64 %45, %44, implicit-def dead $scc
[all …]
Dmerge-load-store-physreg.mir61 %11:sgpr_32 = S_ADD_U32 %10, 4, implicit-def $scc
62 %12:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
109 %21:sgpr_32 = S_ADD_U32 %20, 4, implicit-def $scc
111 %11:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
Dcoalescer-subranges-another-copymi-not-live.mir30 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
40 S_CBRANCH_SCC0 %bb.4, implicit undef $scc
67 S_CBRANCH_SCC0 %bb.8, implicit undef $scc
81 S_CBRANCH_SCC1 %bb.11, implicit undef $scc
89 %23:sreg_64 = S_AND_B64 %22, %21, implicit-def dead $scc
94 $exec = S_OR_B64 $exec, killed %22, implicit-def $scc
114 S_CBRANCH_SCC1 %bb.15, implicit undef $scc
Dwaitcnt-back-edge-loop.mir33 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
40 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
49 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
83 S_CBRANCH_SCC0 %bb.2, implicit $scc
87 S_CBRANCH_SCC0 %bb.2, implicit $scc
91 S_CBRANCH_SCC1 %bb.0, implicit $scc
Ddead_copy.mir20 $sgpr14 = S_ADD_U32 $sgpr0, target-flags(amdgpu-gotprel) 1136, implicit-def $scc
21 …r15 = S_ADDC_U32 $sgpr1, target-flags(amdgpu-gotprel32-lo) 0, implicit-def dead $scc, implicit $scc
Dundefined-physreg-sgpr-spill.mir22 # CHECK-NEXT: $sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
53 $sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
71 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
85 # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
116 $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
135 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
Dsi-fix-sgpr-copies.mir29 %1 = SI_IF %10, %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
33 SI_END_CF %1, implicit-def $exec, implicit-def $scc, implicit $exec
35 %2 = S_ADD_I32 %0, %11, implicit-def $scc
/external/grpc-grpc/test/core/util/
Ddebugger_macros.cc39 grpc_subchannel_call* scc = grpc_client_channel_get_subchannel_call(el); in grpc_transport_stream_from_call() local
40 if (scc == nullptr) { in grpc_transport_stream_from_call()
45 cs = grpc_subchannel_call_get_call_stack(scc); in grpc_transport_stream_from_call()

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