Searched refs:scheduling (Results 1 – 25 of 449) sorted by relevance
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5 2 YES * Because the default scheduling policy is implementation6 dependent, the case only will only demo the scheduling
135 Disable scheduling after register allocation.160 =none: No scheduling: breadth first sequencing161 =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization162 =simple-noitin: Simple two pass scheduling: Same as simple except using generic latency163 =list-burr: Bottom-up register reduction list scheduling164 =list-tdrr: Top-down register reduction list scheduling
25 scheduling models. To that end, we also provide analysis of the results.115 inconsistencies in the scheduling information. The output is an html file. For121 Note that the scheduling class names will be resolved only when
141 Disable scheduling after register allocation.167 =none: No scheduling: breadth first sequencing 168 =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization 169 =simple-noitin: Simple two pass scheduling: Same as simple except using generic latency 170 =list-burr: Bottom-up register reduction list scheduling 171 =list-tdrr: Top-down register reduction list scheduling
1 TITLE: BUG: scheduling while atomic: syz-executor/ADDR3 [ 185.479466] BUG: scheduling while atomic: syz-executor0/19425/0x00000000
8 ; Check that no scheduling dependencies are created between the paired loads and the store during p…
1 ; Without list-burr scheduling we may not see the difference in codegen here.2 ; Use a subtarget that has post-RA scheduling enabled because the anti-dependency
26 ; works because, with new scheduling freedom, we create a copy of R3 based on the27 ; initial scheduling, but don't coalesce it again after we move the instructions
10 // This file defines the target-independent scheduling interfaces12 // itineraries for scheduling. Itineraries are details reservation14 // in-order machine with complicated scheduling or bundling constraints.23 // during scheduling and has an affect instruction order based on availability
10 // This file defines the target-independent scheduling interfaces which should11 // be implemented by each target which is using TableGen based scheduling.94 // that have a scheduling class (itinerary class or SchedRW list)117 // to skip the checks for scheduling information when building LLVM for171 // an in-order pipeline within an out-of-order core where scheduling261 // Allow a processor to mark some scheduling classes as unsupported264 // Allow a processor to mark some scheduling classes as single-issue.320 // Allow a processor to mark some scheduling classes as unsupported357 // Base class for scheduling predicates.360 // A scheduling predicate whose logic is defined by a MCInstPredicate.[all …]
34 ; This is a problem for scheduling the reads from the local data share (lds).83 ; expanding them after scheduling. Once the scheduler has better alias85 ; scheduling.
84 The program runs with the scheduling policy of SCHED_FIFO at a maximum122 - The scheduling policies of threads are different from previous testcase150 wake-up with condvars. Testcase exhibit scheduling of threads in accordance190 - Measures scheduling jitter between realtime processes.196 - Measures the latency involved with periodic scheduling. A thread is created
10 // This file defines the target-independent scheduling interfaces which should11 // be implemented by each target which is using TableGen based scheduling.20 // during scheduling and has an affect instruction order based on availability
3 summary: "Does nothing. Serves as a control trigger for scheduling."
3 # CHECK: error: unable to find instruction-level scheduling information for target triple 'x86_64-u…
6 ; Test if the budget for the scheduling region size works.34 ; some unrelated instructions inbetween to enlarge the scheduling region
3 This test measures scheduling jitter w/ realtime processes.
5 ; We need second, post-ra scheduling to have VSTM instruction combined from single-stores