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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dscvtf.s10 scvtf z0.h, p0/m, z0.h label
16 scvtf z0.h, p0/m, z0.s label
22 scvtf z0.h, p0/m, z0.d label
28 scvtf z0.s, p0/m, z0.s label
34 scvtf z0.s, p0/m, z0.d label
40 scvtf z0.d, p0/m, z0.s label
46 scvtf z0.d, p0/m, z0.d label
62 scvtf z5.d, p0/m, z0.d label
74 scvtf z5.d, p0/m, z0.d label
Dscvtf-diagnostics.s3 scvtf z0.s, p0/m, z0.h label
8 scvtf z0.d, p0/m, z0.h label
17 scvtf z0.h, p8/m, z0.h label
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dsitofp-fixed-legal.ll17 ; CHECK-DAG: scvtf.2d v0, [[BLOCK0_LO]]
18 ; CHECK-DAG: scvtf.2d v1, [[BLOCK0_HI]]
19 ; CHECK-DAG: scvtf.2d v2, [[BLOCK1_LO]]
20 ; CHECK-DAG: scvtf.2d v3, [[BLOCK1_HI]]
21 ; CHECK-DAG: scvtf.2d v4, [[BLOCK2_LO]]
22 ; CHECK-DAG: scvtf.2d v5, [[BLOCK2_HI]]
23 ; CHECK-DAG: scvtf.2d v6, [[BLOCK3_LO]]
24 ; CHECK-DAG: scvtf.2d v7, [[BLOCK3_HI]]
36 ; CHECK-DAG: scvtf.2d v0, v0
37 ; CHECK-DAG: scvtf.2d v1, v1
Dfp16-v16-instructions.ll6 ; CHECK-DAG: scvtf [[S0:v[0-9]+\.4s]], v0.4s
7 ; CHECK-DAG: scvtf [[S1:v[0-9]+\.4s]], v1.4s
8 ; CHECK-DAG: scvtf [[S2:v[0-9]+\.4s]], v2.4s
9 ; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s
24 ; CHECK-DAG: scvtf [[D0:v[0-9]+\.2d]], v0.2d
25 ; CHECK-DAG: scvtf [[D1:v[0-9]+\.2d]], v1.2d
26 ; CHECK-DAG: scvtf [[D2:v[0-9]+\.2d]], v2.2d
27 ; CHECK-DAG: scvtf [[D3:v[0-9]+\.2d]], v3.2d
28 ; CHECK-DAG: scvtf [[D4:v[0-9]+\.2d]], v4.2d
29 ; CHECK-DAG: scvtf [[D5:v[0-9]+\.2d]], v5.2d
[all …]
Dcomplex-int-to-fp.ll4 ; CHECK: scvtf
16 ; CHECK-NEXT: scvtf.2d v0, [[VAL64]]
36 ; CHECK: scvtf.2d v0, [[VAL64]]
57 ; CHECK: scvtf.2d v0, [[VAL64]]
75 ; CHECK: scvtf.2d [[VAL64:v[0-9]+]], v0
94 ; CHECK: scvtf.2s v0, [[VAL32]]
113 ; CHECK: scvtf.2s v0, [[VAL32]]
131 ; CHECK: scvtf.4s v0, [[VAL32]]
151 ; CHECK: scvtf.4s v0, [[VAL32]]
Darm64-scvt.ll9 ; CHECK: scvtf s0, s0
29 ; CHECK: scvtf d0, d0
50 ; CHECK: scvtf d0, [[REG]]
411 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
415 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
429 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
442 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
456 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
472 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
476 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
[all …]
Dfcvt-fixed.ll110 ; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #7
115 ; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #32
120 ; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #7
125 ; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #64
130 ; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #7
135 ; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #32
140 ; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #7
145 ; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #64
Dfdiv_combine.ll5 ; CHECK: scvtf.2s v0, v0, #4
27 ; CHECK: scvtf.2s v0, v0
40 ; CHECK: scvtf.2s v0, v0
53 ; CHECK: scvtf.2s v0, v0, #32
64 ; CHECK: scvtf.4s v0, v0, #2
87 ; CHECK: scvtf.4s v0, v0, #2
Darm64-fast-isel-conversion-fallback.ll30 ; CHECK: scvtf s0, w0
41 ; CHECK: scvtf s0, w0
52 ; CHECK: scvtf s0, w0
62 ; CHECK: scvtf s0, w0
72 ; CHECK: scvtf s0, x0
Dfcvt-int.ll69 ; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}}
83 ; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}}
97 ; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}}
111 ; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}}
Darm64-setcc-int-to-fp-combine.ll20 ; CHECK: scvtf.2d
21 ; CHECK: scvtf.2d
/external/llvm/test/CodeGen/AArch64/
Dfp16-v16-instructions.ll6 ; CHECK-DAG: scvtf [[S0:v[0-9]+\.4s]], v0.4s
7 ; CHECK-DAG: scvtf [[S1:v[0-9]+\.4s]], v1.4s
8 ; CHECK-DAG: scvtf [[S2:v[0-9]+\.4s]], v2.4s
9 ; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s
24 ; CHECK-DAG: scvtf [[D0:v[0-9]+\.2d]], v0.2d
25 ; CHECK-DAG: scvtf [[D1:v[0-9]+\.2d]], v1.2d
26 ; CHECK-DAG: scvtf [[D2:v[0-9]+\.2d]], v2.2d
27 ; CHECK-DAG: scvtf [[D3:v[0-9]+\.2d]], v3.2d
28 ; CHECK-DAG: scvtf [[D4:v[0-9]+\.2d]], v4.2d
29 ; CHECK-DAG: scvtf [[D5:v[0-9]+\.2d]], v5.2d
[all …]
Dcomplex-int-to-fp.ll4 ; CHECK: scvtf
16 ; CHECK-NEXT: scvtf.2d v0, [[VAL64]]
36 ; CHECK: scvtf.2d v0, [[VAL64]]
57 ; CHECK: scvtf.2d v0, [[VAL64]]
75 ; CHECK: scvtf.2d [[VAL64:v[0-9]+]], v0
94 ; CHECK: scvtf.2s v0, [[VAL32]]
113 ; CHECK: scvtf.2s v0, [[VAL32]]
131 ; CHECK: scvtf.4s v0, [[VAL32]]
151 ; CHECK: scvtf.4s v0, [[VAL32]]
Darm64-scvt.ll9 ; CHECK: scvtf s0, s0
29 ; CHECK: scvtf d0, d0
50 ; CHECK: scvtf d0, [[REG]]
411 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
415 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
429 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
442 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
456 ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
472 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
476 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
[all …]
Dfcvt-fixed.ll110 ; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #7
115 ; CHECK: scvtf {{s[0-9]+}}, {{w[0-9]+}}, #32
120 ; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #7
125 ; CHECK: scvtf {{s[0-9]+}}, {{x[0-9]+}}, #64
130 ; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #7
135 ; CHECK: scvtf {{d[0-9]+}}, {{w[0-9]+}}, #32
140 ; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #7
145 ; CHECK: scvtf {{d[0-9]+}}, {{x[0-9]+}}, #64
Dfdiv_combine.ll5 ; CHECK: scvtf.2s v0, v0, #4
27 ; CHECK: scvtf.2s v0, v0
40 ; CHECK: scvtf.2s v0, v0
53 ; CHECK: scvtf.2s v0, v0, #32
64 ; CHECK: scvtf.4s v0, v0, #2
87 ; CHECK: scvtf.4s v0, v0, #2
Darm64-fast-isel-conversion-fallback.ll30 ; CHECK: scvtf s0, w0
41 ; CHECK: scvtf s0, w0
52 ; CHECK: scvtf s0, w0
62 ; CHECK: scvtf s0, w0
72 ; CHECK: scvtf s0, x0
Dfcvt-int.ll69 ; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}}
83 ; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}}
97 ; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}}
111 ; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s9 scvtf h23, h14
10 scvtf s22, s13
11 scvtf d21, d12
33 scvtf h22, h13, #16
34 scvtf s22, s13, #32
35 scvtf d21, d12, #64
Darm64-fp-encoding.s466 scvtf h1, w2
467 scvtf h1, w2, #1
468 scvtf s1, w2
469 scvtf s1, w2, #1
470 scvtf d1, w2 define
471 scvtf d1, w2, #1 define
472 scvtf h1, x2
473 scvtf h1, x2, #1
474 scvtf s1, x2
475 scvtf s1, x2, #1
[all …]
Dneon-simd-shift.s403 scvtf v0.4h, v1.4h, #3
404 scvtf v0.8h, v1.8h, #3
405 scvtf v0.2s, v1.2s, #3
406 scvtf v0.4s, v1.4s, #3
407 scvtf v0.2d, v1.2d, #3
/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s9 scvtf h23, h14
10 scvtf s22, s13
11 scvtf d21, d12
33 scvtf h22, h13, #16
34 scvtf s22, s13, #32
35 scvtf d21, d12, #64
Darm64-fp-encoding.s466 scvtf h1, w2
467 scvtf h1, w2, #1
468 scvtf s1, w2
469 scvtf s1, w2, #1
470 scvtf d1, w2 define
471 scvtf d1, w2, #1 define
472 scvtf h1, x2
473 scvtf h1, x2, #1
474 scvtf s1, x2
475 scvtf s1, x2, #1
[all …]
Dneon-simd-shift.s403 scvtf v0.4h, v1.4h, #3
404 scvtf v0.8h, v1.8h, #3
405 scvtf v0.2s, v1.2s, #3
406 scvtf v0.4s, v1.4s, #3
407 scvtf v0.2d, v1.2d, #3
/external/capstone/suite/MC/AArch64/
Dneon-scalar-cvt.s.cs2 0xb6,0xd9,0x21,0x5e = scvtf s22, s13
3 0x95,0xd9,0x61,0x5e = scvtf d21, d12
6 0xb6,0xe5,0x20,0x5f = scvtf s22, s13, #32
7 0x95,0xe5,0x40,0x5f = scvtf d21, d12, #64

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