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/external/iproute2/tc/
Df_u32.c119 static int pack_key(struct tc_u32_sel *sel, __u32 key, __u32 mask, in pack_key() argument
123 int hwm = sel->nkeys; in pack_key()
128 if (sel->keys[i].off == off && sel->keys[i].offmask == offmask) { in pack_key()
129 __u32 intersect = mask & sel->keys[i].mask; in pack_key()
131 if ((key ^ sel->keys[i].val) & intersect) in pack_key()
133 sel->keys[i].val |= key; in pack_key()
134 sel->keys[i].mask |= mask; in pack_key()
143 sel->keys[hwm].val = key; in pack_key()
144 sel->keys[hwm].mask = mask; in pack_key()
145 sel->keys[hwm].off = off; in pack_key()
[all …]
Dm_pedit.c62 struct m_pedit_sel *sel, in pedit_parse_nopopt() argument
124 struct tc_pedit_sel *sel = &_sel->sel; in pack_key() local
126 int hwm = sel->nkeys; in pack_key()
136 sel->keys[hwm].val = tkey->val; in pack_key()
137 sel->keys[hwm].mask = tkey->mask; in pack_key()
138 sel->keys[hwm].off = tkey->off; in pack_key()
139 sel->keys[hwm].at = tkey->at; in pack_key()
140 sel->keys[hwm].offmask = tkey->offmask; in pack_key()
141 sel->keys[hwm].shift = tkey->shift; in pack_key()
155 sel->nkeys++; in pack_key()
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Dm_csum.c39 parse_csum_args(int *argc_p, char ***argv_p, struct tc_csum *sel) in parse_csum_args() argument
51 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_IPV4HDR; in parse_csum_args()
54 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_ICMP; in parse_csum_args()
57 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_IGMP; in parse_csum_args()
60 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_TCP; in parse_csum_args()
63 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_UDP; in parse_csum_args()
66 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_UDPLITE; in parse_csum_args()
69 sel->update_flags |= TCA_CSUM_UPDATE_FLAG_SCTP; in parse_csum_args()
91 struct tc_csum sel = {}; in parse_csum() local
101 if (parse_csum_args(&argc, &argv, &sel)) { in parse_csum()
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Dm_nat.c44 parse_nat_args(int *argc_p, char ***argv_p, struct tc_nat *sel) in parse_nat_args() argument
54 sel->flags |= TCA_NAT_FLAG_EGRESS; in parse_nat_args()
63 sel->old_addr = addr.data[0]; in parse_nat_args()
64 sel->mask = htonl(~0u << (32 - addr.bitlen)); in parse_nat_args()
71 sel->new_addr = addr.data[0]; in parse_nat_args()
87 struct tc_nat sel = {}; in parse_nat() local
97 if (parse_nat_args(&argc, &argv, &sel)) { in parse_nat()
118 parse_action_control_dflt(&argc, &argv, &sel.action, false, TC_ACT_OK); in parse_nat()
123 if (get_u32(&sel.index, *argv, 10)) { in parse_nat()
134 addattr_l(n, MAX_MSG, TCA_NAT_PARMS, &sel, sizeof(sel)); in parse_nat()
[all …]
Dp_ip.c28 struct m_pedit_sel *sel, struct m_pedit_key *tkey) in parse_ip() argument
37 tkey->htype = sel->extended ? in parse_ip()
44 res = parse_cmd(&argc, &argv, 4, TIPV4, RU32, sel, tkey); in parse_ip()
50 res = parse_cmd(&argc, &argv, 4, TIPV4, RU32, sel, tkey); in parse_ip()
60 res = parse_cmd(&argc, &argv, 1, TU32, RU8, sel, tkey); in parse_ip()
66 res = parse_cmd(&argc, &argv, 1, TU32, 0x0f, sel, tkey); in parse_ip()
72 res = parse_cmd(&argc, &argv, 1, TU32, RU8, sel, tkey); in parse_ip()
78 res = parse_cmd(&argc, &argv, 1, TU32, RU8, sel, tkey); in parse_ip()
85 res = parse_cmd(&argc, &argv, 1, TU32, RU8, sel, tkey); in parse_ip()
92 res = parse_cmd(&argc, &argv, 1, TU32, 0x3F, sel, tkey); in parse_ip()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dcombine-min-max.ll11 %sel = select i1 %cmp, i32 %a, i32 %b
12 ret i32 %sel
20 %sel = select i1 %cmp, i64 %b, i64 %a
21 ret i64 %sel
32 %sel = select i1 %cmp, i16 %a, i16 %b
33 ret i16 %sel
40 %sel = select i1 %cmp, i16 %a, i16 %b
41 ret i16 %sel
48 %sel = select i1 %cmp, i16 %a, i16 %b
49 ret i16 %sel
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dcombine-min-max.ll11 %sel = select i1 %cmp, i32 %a, i32 %b
12 ret i32 %sel
20 %sel = select i1 %cmp, i64 %b, i64 %a
21 ret i64 %sel
34 %sel = select i1 %cmp, i16 %a, i16 %b
35 ret i16 %sel
47 %sel = select i1 %cmp, i32 %a, i32 %b
48 ret i32 %sel
55 %sel = select i1 %cmp, i32 %a, i32 %b
56 ret i32 %sel
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dunordered-fcmp-select.ll5 ; CHECK-NEXT: %sel = select i1 %cmp.inv, float %b, float %a
6 ; CHECK-NEXT: ret float %sel
9 %sel = select i1 %cmp, float %a, float %b
10 ret float %sel
15 ; CHECK-NEXT: %sel = select i1 %cmp.inv, float %b, float %a
16 ; CHECK-NEXT: ret float %sel
19 %sel = select i1 %cmp, float %a, float %b
20 ret float %sel
25 ; CHECK-NEXT: %sel = select i1 %cmp.inv, float %a, float %b
26 ; CHECK-NEXT: ret float %sel
[all …]
Dsmin-icmp.ll18 %sel = select i1 %cmp1, i32 %x, i32 %y
19 %cmp2 = icmp eq i32 %sel, %x
31 %sel = select i1 %cmp1, i32 %y, i32 %x
32 %cmp2 = icmp eq i32 %sel, %x
46 %sel = select i1 %cmp1, i32 %x, i32 %y
47 %cmp2 = icmp eq i32 %x, %sel
61 %sel = select i1 %cmp1, i32 %y, i32 %x
62 %cmp2 = icmp eq i32 %x, %sel
74 %sel = select i1 %cmp1, i32 %x, i32 %y
75 %cmp2 = icmp sge i32 %sel, %x
[all …]
/external/llvm/test/Transforms/InstCombine/
Dunordered-fcmp-select.ll5 ; CHECK-NEXT: %sel = select i1 %cmp.inv, float %b, float %a
6 ; CHECK-NEXT: ret float %sel
9 %sel = select i1 %cmp, float %a, float %b
10 ret float %sel
15 ; CHECK-NEXT: %sel = select i1 %cmp.inv, float %b, float %a
16 ; CHECK-NEXT: ret float %sel
19 %sel = select i1 %cmp, float %a, float %b
20 ret float %sel
25 ; CHECK-NEXT: %sel = select i1 %cmp.inv, float %a, float %b
26 ; CHECK-NEXT: ret float %sel
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/external/llvm/test/Analysis/CostModel/X86/
Dvselect-cost.ll14 ; SSE2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
15 ; SSE41: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
16 ; AVX: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
17 ; AVX2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
18 %sel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
19 ret <2 x i64> %sel
24 ; SSE2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
25 ; SSE41: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
26 ; AVX: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
27 ; AVX2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
[all …]
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_shaders.c48 static void *si_get_tgsi_binary(struct si_shader_selector *sel) in si_get_tgsi_binary() argument
50 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) * in si_get_tgsi_binary()
52 unsigned size = 4 + tgsi_size + sizeof(sel->so); in si_get_tgsi_binary()
59 memcpy(result + 4, sel->tokens, tgsi_size); in si_get_tgsi_binary()
60 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so)); in si_get_tgsi_binary()
406 struct si_shader_selector *sel, in polaris_set_vgt_vertex_reuse() argument
410 unsigned type = sel->type; in polaris_set_vgt_vertex_reuse()
424 sel->info.properties[TGSI_PROPERTY_TES_SPACING] == in polaris_set_vgt_vertex_reuse()
686 struct si_shader_selector *sel = shader->selector; in si_shader_gs() local
687 const ubyte *num_components = sel->info.num_stream_output_components; in si_shader_gs()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/SystemZ/
Dcmpsel.ll11 %sel = select i1 %cmp, i8 %val3, i8 %val4
12 ret i8 %sel
16 ; CHECK: cost of 1 for instruction: %sel = select i1 %cmp, i8 %val3, i8 %val4
22 %sel = select i1 %cmp, i16 %val3, i16 %val4
23 ret i16 %sel
27 ; CHECK: cost of 1 for instruction: %sel = select i1 %cmp, i16 %val3, i16 %val4
33 %sel = select i1 %cmp, i32 %val3, i32 %val4
34 ret i32 %sel
38 ; CHECK: cost of 1 for instruction: %sel = select i1 %cmp, i32 %val3, i32 %val4
44 %sel = select i1 %cmp, i64 %val3, i64 %val4
[all …]
Dscalar-cmp-cmp-log-sel.ll10 %sel = select i1 %and, i8 %val5, i8 %val6
11 ret i8 %sel
17 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i8 %val5, i8 %val6
25 %sel = select i1 %and, i16 %val5, i16 %val6
26 ret i16 %sel
32 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i16 %val5, i16 %val6
40 %sel = select i1 %and, i32 %val5, i32 %val6
41 ret i32 %sel
47 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i32 %val5, i32 %val6
55 %sel = select i1 %and, i64 %val5, i64 %val6
[all …]
/external/libnl/lib/route/cls/
Du32.c119 struct tc_u32_sel *sel; in u32_msg_parser() local
127 sel = u->cu_selector->d_data; in u32_msg_parser()
129 (sel->nkeys * sizeof(uint64_t)); in u32_msg_parser()
205 static void print_selector(struct nl_dump_params *p, struct tc_u32_sel *sel, in print_selector() argument
211 if (sel->hmask || sel->hoff) { in print_selector()
216 nl_dump(p, " hash at %u & 0x%x", sel->hoff, sel->hmask); in print_selector()
219 if (sel->flags & (TC_U32_OFFSET | TC_U32_VAROFFSET)) { in print_selector()
220 nl_dump(p, " offset at %u", sel->off); in print_selector()
222 if (sel->flags & TC_U32_VAROFFSET) in print_selector()
224 sel->offoff, ntohs(sel->offmask), sel->offshift); in print_selector()
[all …]
/external/icu/icu4c/source/common/
Ducnvsel.cpp230 ucnvsel_close(UConverterSelector *sel) { in ucnvsel_close() argument
231 if (!sel) { in ucnvsel_close()
234 if (sel->ownEncodingStrings) { in ucnvsel_close()
235 uprv_free(sel->encodings[0]); in ucnvsel_close()
237 uprv_free(sel->encodings); in ucnvsel_close()
238 if (sel->ownPv) { in ucnvsel_close()
239 uprv_free(sel->pv); in ucnvsel_close()
241 utrie2_close(sel->trie); in ucnvsel_close()
242 uprv_free(sel->swapped); in ucnvsel_close()
243 uprv_free(sel); in ucnvsel_close()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dselect_const.ll16 %sel = select i1 %cond, i32 0, i32 1
17 ret i32 %sel
26 %sel = select i1 %cond, i32 0, i32 1
27 ret i32 %sel
37 %sel = select i1 %cond, i32 0, i32 1
38 ret i32 %sel
49 %sel = select i1 %cond, i32 1, i32 0
50 ret i32 %sel
58 %sel = select i1 %cond, i32 1, i32 0
59 ret i32 %sel
[all …]
Dcmov-fp.ll9 %sel = select i1 %cmp, double 99.0, double %x
10 ret double %sel
28 %sel = select i1 %cmp, double 99.0, double %x
29 ret double %sel
46 %sel = select i1 %cmp, double 99.0, double %x
47 ret double %sel
64 %sel = select i1 %cmp, double 99.0, double %x
65 ret double %sel
82 %sel = select i1 %cmp, double 99.0, double %x
83 ret double %sel
[all …]
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_finalize.cpp325 n->bc.dst_gpr = fdst.sel(); in finalize_alu_group()
331 update_ngpr(d->array->gpr.sel() + d->array->array_size -1); in finalize_alu_group()
386 src.sel = sc.sel(); in finalize_alu_src()
390 update_ngpr(v->array->gpr.sel() + v->array->array_size -1); in finalize_alu_src()
394 if (pn->bc.dst_gpr == src.sel) { in finalize_alu_src()
406 src.sel = gpr.sel(); in finalize_alu_src()
408 update_ngpr(src.sel); in finalize_alu_src()
411 src.sel = v->gpr.sel(); in finalize_alu_src()
413 update_ngpr(src.sel); in finalize_alu_src()
421 src.sel = ALU_SRC_0; in finalize_alu_src()
[all …]
/external/llvm/test/CodeGen/X86/
Dcmov-fp.ll9 %sel = select i1 %cmp, double 99.0, double %x
10 ret double %sel
28 %sel = select i1 %cmp, double 99.0, double %x
29 ret double %sel
46 %sel = select i1 %cmp, double 99.0, double %x
47 ret double %sel
64 %sel = select i1 %cmp, double 99.0, double %x
65 ret double %sel
82 %sel = select i1 %cmp, double 99.0, double %x
83 ret double %sel
[all …]
/external/llvm/test/Transforms/CodeGenPrepare/X86/
Dselect.ll11 %sel = select i1 %cmp, i32 %x, i32 %y
12 ret i32 %sel
17 ; CHECK: %sel = select i1 %cmp, i32 %x, i32 %y
18 ; CHECK: ret i32 %sel
28 %sel = select i1 %cmp, float %div, float 2.0
29 ret float %sel
38 ; CHECK: %sel = phi float [ %div, %select.true.sink ], [ 2.000000e+00, %entry ]
39 ; CHECK: ret float %sel
46 %sel = select i1 %cmp, float 4.0, float %div
47 ret float %sel
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dselect_const.ll15 %sel = select i1 %cond, i32 0, i32 1
16 ret i32 %sel
24 %sel = select i1 %cond, i32 0, i32 1
25 ret i32 %sel
34 %sel = select i1 %cond, i32 0, i32 1
35 ret i32 %sel
45 %sel = select i1 %cond, i32 1, i32 0
46 ret i32 %sel
53 %sel = select i1 %cond, i32 1, i32 0
54 ret i32 %sel
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/X86/
Dvselect-cost.ll15 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sel = select <2 x i1> <i1…
16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %sel
18 %sel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
19 ret <2 x i64> %sel
24 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sel = select <2 x i1> <i1…
25 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %sel
27 %sel = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
28 ret <2 x double> %sel
33 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sel = select <4 x i1> <i1…
34 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %sel
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/AArch64/
Dshuffle-select.ll4 ; COST-LABEL: sel.v8i8
6 ; CODE-LABEL: sel.v8i8
8 define <8 x i8> @sel.v8i8(<8 x i8> %v0, <8 x i8> %v1) {
13 ; COST-LABEL: sel.v16i8
15 ; CODE-LABEL: sel.v16i8
17 define <16 x i8> @sel.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
22 ; COST-LABEL: sel.v4i16
24 ; CODE-LABEL: sel.v4i16
27 define <4 x i16> @sel.v4i16(<4 x i16> %v0, <4 x i16> %v1) {
32 ; COST-LABEL: sel.v8i16
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dselect_const.ll16 %sel = select i1 %cond, i32 0, i32 1
17 ret i32 %sel
25 %sel = select i1 %cond, i32 0, i32 1
26 ret i32 %sel
35 %sel = select i1 %cond, i32 0, i32 1
36 ret i32 %sel
46 %sel = select i1 %cond, i32 1, i32 0
47 ret i32 %sel
54 %sel = select i1 %cond, i32 1, i32 0
55 ret i32 %sel
[all …]

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