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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dmachine-combiner.ll384 %sel1 = select i1 %cmp1, float %x2, float %t0
385 %cmp2 = fcmp olt float %x3, %sel1
386 %sel2 = select i1 %cmp2, float %x3, float %sel1
408 %sel1 = select i1 %cmp1, float %x2, float %t0
409 %cmp2 = fcmp ogt float %x3, %sel1
410 %sel2 = select i1 %cmp2, float %x3, float %sel1
432 %sel1 = select i1 %cmp1, double %x2, double %t0
433 %cmp2 = fcmp olt double %x3, %sel1
434 %sel2 = select i1 %cmp2, double %x3, double %sel1
456 %sel1 = select i1 %cmp1, double %x2, double %t0
[all …]
Dpr22338.ll42 %sel1 = select i1 %cmp1, i32 0, i32 2
45 %shl1 = shl i32 %sext, %sel1
/external/llvm/test/CodeGen/X86/
Dmachine-combiner.ll379 %sel1 = select i1 %cmp1, float %x2, float %t0
380 %cmp2 = fcmp olt float %x3, %sel1
381 %sel2 = select i1 %cmp2, float %x3, float %sel1
403 %sel1 = select i1 %cmp1, float %x2, float %t0
404 %cmp2 = fcmp ogt float %x3, %sel1
405 %sel2 = select i1 %cmp2, float %x3, float %sel1
427 %sel1 = select i1 %cmp1, double %x2, double %t0
428 %cmp2 = fcmp olt double %x3, %sel1
429 %sel2 = select i1 %cmp2, double %x3, double %sel1
451 %sel1 = select i1 %cmp1, double %x2, double %t0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dselect-select.ll27 ; CHECK: %[[sel1:.*]] = select i1 %bool, <2 x i32> %[[sel0]], <2 x i32> %V
28 ; CHECK: ret <2 x i32> %[[sel1]]
30 %sel1 = select i1 %bool, <2 x i32> %sel0, <2 x i32> %V
31 ret <2 x i32> %sel1
Dpr36362.ll12 %sel1 = select i1 %a, i32 %b, i32 -1
13 %rem = srem i32 %c, %sel1
Dzext-bool-add-sub.ll29 %sel1 = select i1 %a, i32 2, i32 1
30 %sel2 = select i1 %b, i32 %sel1, i32 %zext
58 %sel1 = select i1 %y, i32 %add1, i32 %frombool
59 %add2 = add nsw i32 %sel1, 1
60 %sel2 = select i1 %z, i32 %add2, i32 %sel1
Dlogical-select.ll78 %sel1 = select i1 %cmp1, i32 %c, i32 0
81 %or = or i32 %sel1, %sel2
97 %sel1 = select i1 %cmp1, i32 0, i32 %c
100 %or = or i32 %sel1, %sel2
116 %sel1 = select i1 %cmp1, i32 %c, i32 0
119 %or = or i32 %sel1, %sel2
135 %sel1 = select <2 x i1> %cmp1, <2 x i32> %c, <2 x i32> <i32 0, i32 0>
138 %or = or <2 x i32> %sel1, %sel2
/external/llvm/test/Transforms/InstCombine/
Dselect-select.ll27 ; CHECK: %[[sel1:.*]] = select i1 %bool, <2 x i32> %[[sel0]], <2 x i32> %V
28 ; CHECK: ret <2 x i32> %[[sel1]]
30 %sel1 = select i1 %bool, <2 x i32> %sel0, <2 x i32> %V
31 ret <2 x i32> %sel1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dsminmax.v2i16.ll165 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
168 store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
181 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
184 store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
196 %sel1 = select <4 x i1> %cond0, <4 x i16> %val1, <4 x i16> %val0
199 store volatile <4 x i16> %sel1, <4 x i16> addrspace(1)* %out1, align 4
210 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
213 store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
224 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
227 store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
Dsminmax.ll199 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
202 store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
218 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
221 store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
237 %sel1 = select <4 x i1> %cond0, <4 x i32> %val1, <4 x i32> %val0
240 store volatile <4 x i32> %sel1, <4 x i32> addrspace(1)* %out1, align 4
255 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
258 store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
/external/llvm/test/CodeGen/AMDGPU/
Dsminmax.ll162 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
165 store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
181 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
184 store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
200 %sel1 = select <4 x i1> %cond0, <4 x i32> %val1, <4 x i32> %val0
203 store volatile <4 x i32> %sel1, <4 x i32> addrspace(1)* %out1, align 4
218 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
221 store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
/external/llvm/test/CodeGen/Hexagon/
Dgp-rel.ll31 %sel1 = select i1 %cmp2, i32 %2, i32 %1
32 ret i32 %sel1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dsignbits.ll31 %sel1 = select i1 %icmp1, i16 %phi0, i16 4
32 ret i16 %sel1
Dasm-18.ll548 %sel1 = select i1 %cmp1, i32 100, i32 200
551 "=h,r,r"(i32 %sel1, i32 %sel2)
688 %sel1 = select i1 %cmp1, i32 0, i32 1
689 %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1)
705 %sel1 = select i1 %cmp1, i32 0, i32 1
706 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1)
723 %sel1 = select i1 %cmp1, i32 0, i32 1
724 %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1)
743 %sel1 = select i1 %cmp1, i32 0, i32 1
744 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dgp-rel.ll31 %sel1 = select i1 %cmp2, i32 %2, i32 %1
32 ret i32 %sel1
/external/llvm/test/Analysis/Lint/
Dcppeh-catch-intrinsics-clean.ll72 %sel1 = extractvalue { i8*, i32 } %l1.0, 1
74 %matchesl1 = icmp eq i32 %sel1, %l1.1
79 %sel2 = phi i32 [%sel, %lpad], [%sel1, %lpad1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/Lint/
Dcppeh-catch-intrinsics-clean.ll72 %sel1 = extractvalue { i8*, i32 } %l1.0, 1
74 %matchesl1 = icmp eq i32 %sel1, %l1.1
79 %sel2 = phi i32 [%sel, %lpad], [%sel1, %lpad1]
/external/clang/test/SemaObjC/
Darc-peformselector.m15 SEL sel1; field
28 …return [self performSelector : sel1]; // expected-warning {{performSelector may cause a leak becau…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Ddag-combine-select.ll17 %sel1 = select i1 %cmp2, i32 %v1, i32 %sel0
18 ret i32 %sel1
/external/llvm/test/CodeGen/AArch64/
Ddag-combine-select.ll17 %sel1 = select i1 %cmp2, i32 %v1, i32 %sel0
18 ret i32 %sel1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/vect/
Dvect-load.ll33 %sel1 = and i1 %cmp23, %cmp25
34 br i1 %sel1, label %while.body, label %while.end422
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-load.ll33 %sel1 = and i1 %cmp23, %cmp25
34 br i1 %sel1, label %while.body, label %while.end422
/external/llvm/test/CodeGen/SystemZ/
Dasm-18.ll544 %sel1 = select i1 %cmp1, i32 100, i32 200
547 "=h,r,r"(i32 %sel1, i32 %sel2)
684 %sel1 = select i1 %cmp1, i32 0, i32 1
685 %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1)
701 %sel1 = select i1 %cmp1, i32 0, i32 1
702 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1)
719 %sel1 = select i1 %cmp1, i32 0, i32 1
720 %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1)
739 %sel1 = select i1 %cmp1, i32 0, i32 1
740 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1)
/external/python/cpython2/Demo/tix/
Dtixwidgets.py380 sel1 = Tix.Select(w, label='Mere Mortals', allowzero=1, radio=1,
389 sel1.add('eat', text='Eat')
390 sel1.add('work', text='Work')
391 sel1.add('play', text='Play')
392 sel1.add('party', text='Party')
393 sel1.add('sleep', text='Sleep')
401 sel1.pack(side=Tix.LEFT, padx=5, pady=3, fill=Tix.X)
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Dpropagate_ir_flags.ll367 %sel1 = select i1 %cmp1, double %load1, double %sub1
370 store double %sel1, double* %idx1, align 8
392 %sel1 = select i1 %cmp1, double %load1, double %sub1
395 store double %sel1, double* %idx1, align 8

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