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/external/llvm/test/CodeGen/NVPTX/
Dcompare-int.ll13 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
22 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
31 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
40 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
49 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
58 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
67 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
76 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
85 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
94 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
[all …]
Di1-int-to-fp.ll5 ; CHECK: selp
14 ; CHECK: selp
23 ; CHECK: selp
32 ; CHECK: selp
Dinline-asm.ll13 ; CHECK: selp.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}}
14 %0 = tail call i32 asm "selp.b32 $0, $1, $2, $3;", "=r,r,r,b"(i32 %a, i32 %b, i1 %cond)
Dadd-128bit.ll11 ; CHECK: selp.b64
12 ; CHECK: selp.b64
Dshift-parts.ll13 ; CHECK: selp.b64
31 ; CHECK: selp.b64
Dbug22246.ll9 ; CHECK: selp.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dcompare-int.ll13 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
22 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
31 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
40 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
49 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
58 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
67 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
76 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
85 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
94 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
[all …]
Di1-int-to-fp.ll5 ; CHECK: selp
14 ; CHECK: selp
23 ; CHECK: selp
32 ; CHECK: selp
Dinline-asm.ll13 ; CHECK: selp.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}}
14 %0 = tail call i32 asm "selp.b32 $0, $1, $2, $3;", "=r,r,r,b"(i32 %a, i32 %b, i1 %cond)
Dadd-128bit.ll11 ; CHECK: selp.u64
12 ; CHECK: selp.b64
Dshift-parts.ll13 ; CHECK: selp.b64
31 ; CHECK: selp.b64
Df16x2-instructions.ll51 ; CHECK: selp.b16 [[R:%h[0-9]+]], [[E0]], [[E1]], [[PRED]];
383 ; CHECK-NEXT: selp.b32 [[R:%hh[0-9]+]], [[A]], [[B]], [[PRED]];
410 ; CHECK-DAG: selp.b16 [[R0:%h[0-9]+]], [[A0]], [[B0]], [[P0]];
411 ; CHECK-DAG: selp.b16 [[R1:%h[0-9]+]], [[A1]], [[B1]], [[P1]];
437 ; CHECK-DAG: selp.f32 [[R0:%f[0-9]+]], [[A0]], [[B0]], [[P0]];
438 ; CHECK-DAG: selp.f32 [[R1:%f[0-9]+]], [[A1]], [[B1]], [[P1]];
457 ; CHECK-DAG: selp.b16 [[R0:%h[0-9]+]], [[A0]], [[B0]], [[P0]];
458 ; CHECK-DAG: selp.b16 [[R1:%h[0-9]+]], [[A1]], [[B1]], [[P1]];
481 ; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
482 ; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
[all …]
Df16-instructions.ll263 ; CHECK-NEXT: selp.b16 [[R:%h[0-9]+]], [[A]], [[B]], [[PRED]];
280 ; CHECK: selp.b16 [[R:%h[0-9]+]], [[A]], [[B]], [[PRED]];
298 ; CHECK-NEXT: selp.f32 [[R:%f[0-9]+]], [[A]], [[B]], [[PRED]];
313 ; CHECK-NEXT: selp.b16 [[R:%h[0-9]+]], [[A]], [[B]], [[PRED]];
329 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
344 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
359 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
374 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
389 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
404 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
[all …]
Dtid-range.ll13 ; CHECK: selp.u32 %[[R:.+]], 1, 0, %p1;
Dbug22246.ll9 ; CHECK: selp.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}}
/external/swiftshader/third_party/LLVM/test/CodeGen/PTX/
Dsetp.ll5 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
14 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
23 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
32 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
41 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
50 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
59 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
68 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
77 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
86 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]];
[all …]
Dselp.ll4 ; CHECK: selp.u32 %ret{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}};
10 ; CHECK: selp.u64 %ret{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}, %p{{[0-9]+}};
16 ; CHECK: selp.f32 %ret{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %p{{[0-9]+}};
22 ; CHECK: selp.f64 %ret{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %p{{[0-9]+}};
Dcvt.ll9 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]];
20 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]];
31 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]];
42 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]];
53 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]];
64 ; CHECK: selp.u16 %ret{{[0-9]+}}, 1, 0, %p{{[0-9]+}};
101 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p{{[0-9]+}};
138 ; CHECK: selp.u64 %ret{{[0-9]+}}, 1, 0, %p{{[0-9]+}};
177 ; CHECK: selp.f32 %ret{{[0-9]+}}, %f0, %f1, %p{{[0-9]+}};
237 ; CHECK: selp.f64 %ret{{[0-9]+}}, %fd0, %fd1, %p{{[0-9]+}};
/external/iproute2/ip/
Dxfrm_policy.c262 char *selp = NULL; in xfrm_policy_modify() local
342 if (selp) in xfrm_policy_modify()
344 selp = *argv; in xfrm_policy_modify()
568 char *selp = NULL; in xfrm_policy_get_or_delete() local
617 if (selp) in xfrm_policy_get_or_delete()
619 selp = *argv; in xfrm_policy_get_or_delete()
638 if (!selp && !indexp) { in xfrm_policy_get_or_delete()
642 if (selp && indexp) in xfrm_policy_get_or_delete()
773 char *selp = NULL; in xfrm_policy_list_or_deleteall() local
829 if (selp) in xfrm_policy_list_or_deleteall()
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1318 // Selection instructions (selp)
1323 // selp instructions that don't have any pattern matches; we explicitly use
1329 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1332 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1335 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1338 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1346 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1351 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1356 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1361 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1454 // Selection instructions (selp)
1459 // selp instructions that don't have any pattern matches; we explicitly use
1465 !strconcat("selp.", TypeStr, " \t$dst, $a, $b, $p;"), []>;
1468 !strconcat("selp.", TypeStr, " \t$dst, $a, $b, $p;"), []>;
1471 !strconcat("selp.", TypeStr, " \t$dst, $a, $b, $p;"), []>;
1474 !strconcat("selp.", TypeStr, " \t$dst, $a, $b, $p;"), []>;
1482 !strconcat("selp.", TypeStr, " \t$dst, $a, $b, $p;"),
1487 !strconcat("selp.", TypeStr, " \t$dst, $a, $b, $p;"),
1492 !strconcat("selp.", TypeStr, " \t$dst, $a, $b, $p;"),
1497 !strconcat("selp.", TypeStr, " \t$dst, $a, $b, $p;"),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXInstrInfo.td464 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
468 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
472 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
602 // .selp
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_lowering_nvc0.cpp1485 Instruction *selp = in handleSharedATOM() local
1488 selp->src(2).mod = Modifier(NV50_IR_MOD_NOT); in handleSharedATOM()
1489 selp->setPredicate(CC_P, ld->getDef(1)); in handleSharedATOM()
1491 stVal = selp->getDef(0); in handleSharedATOM()
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DNVPTXUsage.rst951 selp.f32 %f99, 0f00000000, %f98, %p15;
953 selp.f32 %f110, 0f7F800000, %f99, %p16;
/external/llvm/docs/
DNVPTXUsage.rst959 selp.f32 %f99, 0f00000000, %f98, %p15;
961 selp.f32 %f110, 0f7F800000, %f99, %p16;

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