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1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
16 
17 #include "llvm/MC/MCCodeGenInfo.h"
18 #include "llvm/ADT/StringRef.h"
19 #include <cassert>
20 #include <string>
21 
22 namespace llvm {
23 
24 class InstrItineraryData;
25 class JITCodeEmitter;
26 class MCAsmInfo;
27 class MCCodeGenInfo;
28 class MCContext;
29 class Pass;
30 class PassManager;
31 class PassManagerBase;
32 class Target;
33 class TargetData;
34 class TargetELFWriterInfo;
35 class TargetFrameLowering;
36 class TargetInstrInfo;
37 class TargetIntrinsicInfo;
38 class TargetJITInfo;
39 class TargetLowering;
40 class TargetRegisterInfo;
41 class TargetSelectionDAGInfo;
42 class TargetSubtargetInfo;
43 class formatted_raw_ostream;
44 class raw_ostream;
45 
46 // Code generation optimization level.
47 namespace CodeGenOpt {
48   enum Level {
49     None,        // -O0
50     Less,        // -O1
51     Default,     // -O2, -Os
52     Aggressive   // -O3
53   };
54 }
55 
56 namespace Sched {
57   enum Preference {
58     None,             // No preference
59     Latency,          // Scheduling for shortest total latency.
60     RegPressure,      // Scheduling for lowest register pressure.
61     Hybrid,           // Scheduling for both latency and register pressure.
62     ILP               // Scheduling for ILP in low register pressure mode.
63   };
64 }
65 
66 //===----------------------------------------------------------------------===//
67 ///
68 /// TargetMachine - Primary interface to the complete machine description for
69 /// the target machine.  All target-specific information should be accessible
70 /// through this interface.
71 ///
72 class TargetMachine {
73   TargetMachine(const TargetMachine &);   // DO NOT IMPLEMENT
74   void operator=(const TargetMachine &);  // DO NOT IMPLEMENT
75 protected: // Can only create subclasses.
76   TargetMachine(const Target &T, StringRef TargetTriple,
77                 StringRef CPU, StringRef FS);
78 
79   /// getSubtargetImpl - virtual method implemented by subclasses that returns
80   /// a reference to that target's TargetSubtargetInfo-derived member variable.
getSubtargetImpl()81   virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
82 
83   /// TheTarget - The Target that this machine was created for.
84   const Target &TheTarget;
85 
86   /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
87   /// feature strings the TargetMachine instance is created with.
88   std::string TargetTriple;
89   std::string TargetCPU;
90   std::string TargetFS;
91 
92   /// CodeGenInfo - Low level target information such as relocation model.
93   const MCCodeGenInfo *CodeGenInfo;
94 
95   /// AsmInfo - Contains target specific asm information.
96   ///
97   const MCAsmInfo *AsmInfo;
98 
99   unsigned MCRelaxAll : 1;
100   unsigned MCNoExecStack : 1;
101   unsigned MCSaveTempLabels : 1;
102   unsigned MCUseLoc : 1;
103   unsigned MCUseCFI : 1;
104 
105 public:
106   virtual ~TargetMachine();
107 
getTarget()108   const Target &getTarget() const { return TheTarget; }
109 
getTargetTriple()110   const StringRef getTargetTriple() const { return TargetTriple; }
getTargetCPU()111   const StringRef getTargetCPU() const { return TargetCPU; }
getTargetFeatureString()112   const StringRef getTargetFeatureString() const { return TargetFS; }
113 
114   // Interfaces to the major aspects of target machine information:
115   // -- Instruction opcode and operand information
116   // -- Pipelines and scheduling information
117   // -- Stack frame information
118   // -- Selection DAG lowering information
119   //
getInstrInfo()120   virtual const TargetInstrInfo         *getInstrInfo() const { return 0; }
getFrameLowering()121   virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
getTargetLowering()122   virtual const TargetLowering    *getTargetLowering() const { return 0; }
getSelectionDAGInfo()123   virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
getTargetData()124   virtual const TargetData             *getTargetData() const { return 0; }
125 
126   /// getMCAsmInfo - Return target specific asm information.
127   ///
getMCAsmInfo()128   const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
129 
130   /// getSubtarget - This method returns a pointer to the specified type of
131   /// TargetSubtargetInfo.  In debug builds, it verifies that the object being
132   /// returned is of the correct type.
getSubtarget()133   template<typename STC> const STC &getSubtarget() const {
134     return *static_cast<const STC*>(getSubtargetImpl());
135   }
136 
137   /// getRegisterInfo - If register information is available, return it.  If
138   /// not, return null.  This is kept separate from RegInfo until RegInfo has
139   /// details of graph coloring register allocation removed from it.
140   ///
getRegisterInfo()141   virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
142 
143   /// getIntrinsicInfo - If intrinsic information is available, return it.  If
144   /// not, return null.
145   ///
getIntrinsicInfo()146   virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
147 
148   /// getJITInfo - If this target supports a JIT, return information for it,
149   /// otherwise return null.
150   ///
getJITInfo()151   virtual TargetJITInfo *getJITInfo() { return 0; }
152 
153   /// getInstrItineraryData - Returns instruction itinerary data for the target
154   /// or specific subtarget.
155   ///
getInstrItineraryData()156   virtual const InstrItineraryData *getInstrItineraryData() const {
157     return 0;
158   }
159 
160   /// getELFWriterInfo - If this target supports an ELF writer, return
161   /// information for it, otherwise return null.
162   ///
getELFWriterInfo()163   virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
164 
165   /// hasMCRelaxAll - Check whether all machine code instructions should be
166   /// relaxed.
hasMCRelaxAll()167   bool hasMCRelaxAll() const { return MCRelaxAll; }
168 
169   /// setMCRelaxAll - Set whether all machine code instructions should be
170   /// relaxed.
setMCRelaxAll(bool Value)171   void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
172 
173   /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
174   /// (i.e., not treated as temporary).
hasMCSaveTempLabels()175   bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
176 
177   /// setMCSaveTempLabels - Set whether temporary labels will be preserved
178   /// (i.e., not treated as temporary).
setMCSaveTempLabels(bool Value)179   void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
180 
181   /// hasMCNoExecStack - Check whether an executable stack is not needed.
hasMCNoExecStack()182   bool hasMCNoExecStack() const { return MCNoExecStack; }
183 
184   /// setMCNoExecStack - Set whether an executabel stack is not needed.
setMCNoExecStack(bool Value)185   void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
186 
187   /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
hasMCUseLoc()188   bool hasMCUseLoc() const { return MCUseLoc; }
189 
190   /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
setMCUseLoc(bool Value)191   void setMCUseLoc(bool Value) { MCUseLoc = Value; }
192 
193   /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
hasMCUseCFI()194   bool hasMCUseCFI() const { return MCUseCFI; }
195 
196   /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
setMCUseCFI(bool Value)197   void setMCUseCFI(bool Value) { MCUseCFI = Value; }
198 
199   /// getRelocationModel - Returns the code generation relocation model. The
200   /// choices are static, PIC, and dynamic-no-pic, and target default.
201   Reloc::Model getRelocationModel() const;
202 
203   /// getCodeModel - Returns the code model. The choices are small, kernel,
204   /// medium, large, and target default.
205   CodeModel::Model getCodeModel() const;
206 
207   /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
208   ///
209   static bool getAsmVerbosityDefault();
210 
211   /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
212   /// is false.
213   static void setAsmVerbosityDefault(bool);
214 
215   /// getDataSections - Return true if data objects should be emitted into their
216   /// own section, corresponds to -fdata-sections.
217   static bool getDataSections();
218 
219   /// getFunctionSections - Return true if functions should be emitted into
220   /// their own section, corresponding to -ffunction-sections.
221   static bool getFunctionSections();
222 
223   /// setDataSections - Set if the data are emit into separate sections.
224   static void setDataSections(bool);
225 
226   /// setFunctionSections - Set if the functions are emit into separate
227   /// sections.
228   static void setFunctionSections(bool);
229 
230   /// CodeGenFileType - These enums are meant to be passed into
231   /// addPassesToEmitFile to indicate what type of file to emit, and returned by
232   /// it to indicate what type of file could actually be made.
233   enum CodeGenFileType {
234     CGFT_AssemblyFile,
235     CGFT_ObjectFile,
236     CGFT_Null         // Do not emit any output.
237   };
238 
239   /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
240   /// on this target.  User flag overrides.
getEnableTailMergeDefault()241   virtual bool getEnableTailMergeDefault() const { return true; }
242 
243   /// addPassesToEmitFile - Add passes to the specified pass manager to get the
244   /// specified file emitted.  Typically this will involve several steps of code
245   /// generation.  This method should return true if emission of this file type
246   /// is not supported, or false on success.
247   virtual bool addPassesToEmitFile(PassManagerBase &,
248                                    formatted_raw_ostream &,
249                                    CodeGenFileType,
250                                    CodeGenOpt::Level,
251                                    bool = true) {
252     return true;
253   }
254 
255   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
256   /// get machine code emitted.  This uses a JITCodeEmitter object to handle
257   /// actually outputting the machine code and resolving things like the address
258   /// of functions.  This method returns true if machine code emission is
259   /// not supported.
260   ///
261   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
262                                           JITCodeEmitter &,
263                                           CodeGenOpt::Level,
264                                           bool = true) {
265     return true;
266   }
267 
268   /// addPassesToEmitMC - Add passes to the specified pass manager to get
269   /// machine code emitted with the MCJIT. This method returns true if machine
270   /// code is not supported. It fills the MCContext Ctx pointer which can be
271   /// used to build custom MCStreamer.
272   ///
273   virtual bool addPassesToEmitMC(PassManagerBase &,
274                                  MCContext *&,
275                                  raw_ostream &,
276                                  CodeGenOpt::Level,
277                                  bool = true) {
278     return true;
279   }
280 };
281 
282 /// LLVMTargetMachine - This class describes a target machine that is
283 /// implemented with the LLVM target-independent code generator.
284 ///
285 class LLVMTargetMachine : public TargetMachine {
286 protected: // Can only create subclasses.
287   LLVMTargetMachine(const Target &T, StringRef TargetTriple,
288                     StringRef CPU, StringRef FS,
289                     Reloc::Model RM, CodeModel::Model CM);
290 
291 private:
292   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
293   /// both emitting to assembly files or machine code output.
294   ///
295   bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
296                               bool DisableVerify, MCContext *&OutCtx);
297 
298 public:
299   /// addPassesToEmitFile - Add passes to the specified pass manager to get the
300   /// specified file emitted.  Typically this will involve several steps of code
301   /// generation.  If OptLevel is None, the code generator should emit code as
302   /// fast as possible, though the generated code may be less efficient.
303   virtual bool addPassesToEmitFile(PassManagerBase &PM,
304                                    formatted_raw_ostream &Out,
305                                    CodeGenFileType FileType,
306                                    CodeGenOpt::Level,
307                                    bool DisableVerify = true);
308 
309   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
310   /// get machine code emitted.  This uses a JITCodeEmitter object to handle
311   /// actually outputting the machine code and resolving things like the address
312   /// of functions.  This method returns true if machine code emission is
313   /// not supported.
314   ///
315   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
316                                           JITCodeEmitter &MCE,
317                                           CodeGenOpt::Level,
318                                           bool DisableVerify = true);
319 
320   /// addPassesToEmitMC - Add passes to the specified pass manager to get
321   /// machine code emitted with the MCJIT. This method returns true if machine
322   /// code is not supported. It fills the MCContext Ctx pointer which can be
323   /// used to build custom MCStreamer.
324   ///
325   virtual bool addPassesToEmitMC(PassManagerBase &PM,
326                                  MCContext *&Ctx,
327                                  raw_ostream &OS,
328                                  CodeGenOpt::Level OptLevel,
329                                  bool DisableVerify = true);
330 
331   /// Target-Independent Code Generator Pass Configuration Options.
332 
333   /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
334   /// passes (which are run just before instruction selector).
addPreISel(PassManagerBase &,CodeGenOpt::Level)335   virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
336     return true;
337   }
338 
339   /// addInstSelector - This method should install an instruction selector pass,
340   /// which converts from LLVM code to machine instructions.
addInstSelector(PassManagerBase &,CodeGenOpt::Level)341   virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
342     return true;
343   }
344 
345   /// addPreRegAlloc - This method may be implemented by targets that want to
346   /// run passes immediately before register allocation. This should return
347   /// true if -print-machineinstrs should print after these passes.
addPreRegAlloc(PassManagerBase &,CodeGenOpt::Level)348   virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
349     return false;
350   }
351 
352   /// addPostRegAlloc - This method may be implemented by targets that want
353   /// to run passes after register allocation but before prolog-epilog
354   /// insertion.  This should return true if -print-machineinstrs should print
355   /// after these passes.
addPostRegAlloc(PassManagerBase &,CodeGenOpt::Level)356   virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
357     return false;
358   }
359 
360   /// addPreSched2 - This method may be implemented by targets that want to
361   /// run passes after prolog-epilog insertion and before the second instruction
362   /// scheduling pass.  This should return true if -print-machineinstrs should
363   /// print after these passes.
addPreSched2(PassManagerBase &,CodeGenOpt::Level)364   virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
365     return false;
366   }
367 
368   /// addPreEmitPass - This pass may be implemented by targets that want to run
369   /// passes immediately before machine code is emitted.  This should return
370   /// true if -print-machineinstrs should print out the code after the passes.
addPreEmitPass(PassManagerBase &,CodeGenOpt::Level)371   virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
372     return false;
373   }
374 
375 
376   /// addCodeEmitter - This pass should be overridden by the target to add a
377   /// code emitter, if supported.  If this is not supported, 'true' should be
378   /// returned.
addCodeEmitter(PassManagerBase &,CodeGenOpt::Level,JITCodeEmitter &)379   virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
380                               JITCodeEmitter &) {
381     return true;
382   }
383 
384   /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
385   /// on this target.  User flag overrides.
getEnableTailMergeDefault()386   virtual bool getEnableTailMergeDefault() const { return true; }
387 };
388 
389 } // End llvm namespace
390 
391 #endif
392