| /external/libunwind/src/dwarf/ |
| D | Gparser.c | 51 set_reg (dwarf_state_record_t *sr, unw_word_t regnum, dwarf_where_t where, in set_reg() function
154 set_reg (sr, regnum, DWARF_WHERE_CFAREL, val * dci->data_align); in run_cfi_program()
163 set_reg (sr, regnum, DWARF_WHERE_CFAREL, val * dci->data_align); in run_cfi_program()
172 set_reg (sr, regnum, DWARF_WHERE_CFAREL, val * dci->data_align); in run_cfi_program()
219 set_reg (sr, regnum, DWARF_WHERE_UNDEF, 0); in run_cfi_program()
226 set_reg (sr, regnum, DWARF_WHERE_SAME, 0); in run_cfi_program()
234 set_reg (sr, regnum, DWARF_WHERE_REG, val); in run_cfi_program()
271 set_reg (sr, DWARF_CFA_REG_COLUMN, DWARF_WHERE_REG, regnum); in run_cfi_program()
272 set_reg (sr, DWARF_CFA_OFF_COLUMN, 0, val); /* NOT factored! */ in run_cfi_program()
280 set_reg (sr, DWARF_CFA_REG_COLUMN, DWARF_WHERE_REG, regnum); in run_cfi_program()
[all …]
|
| /external/linux-kselftest/tools/testing/selftests/kvm/lib/aarch64/ |
| D | processor.c | 247 set_reg(vm, vcpuid, ARM64_CORE_REG(sp_el1), stack_vaddr + stack_size); in vm_vcpu_add_default()
248 set_reg(vm, vcpuid, ARM64_CORE_REG(regs.pc), (uint64_t)guest_code); in vm_vcpu_add_default()
264 set_reg(vm, vcpuid, ARM64_SYS_REG(CPACR_EL1), 3 << 20); in vcpu_setup()
295 set_reg(vm, vcpuid, ARM64_SYS_REG(SCTLR_EL1), sctlr_el1); in vcpu_setup()
296 set_reg(vm, vcpuid, ARM64_SYS_REG(TCR_EL1), tcr_el1); in vcpu_setup()
297 set_reg(vm, vcpuid, ARM64_SYS_REG(MAIR_EL1), DEFAULT_MAIR_EL1); in vcpu_setup()
298 set_reg(vm, vcpuid, ARM64_SYS_REG(TTBR0_EL1), vm->pgd); in vcpu_setup()
|
| /external/u-boot/drivers/ram/stm32mp1/ |
| D | stm32mp1_ddr.c | 224 static void set_reg(const struct ddr_info *priv, in set_reg() function
416 set_reg(priv, REG_REG, &config->c_reg); in stm32mp1_ddr_init()
417 set_reg(priv, REG_TIMING, &config->c_timing); in stm32mp1_ddr_init()
418 set_reg(priv, REG_MAP, &config->c_map); in stm32mp1_ddr_init()
425 set_reg(priv, REG_PERF, &config->c_perf); in stm32mp1_ddr_init()
435 set_reg(priv, REGPHY_REG, &config->p_reg); in stm32mp1_ddr_init()
436 set_reg(priv, REGPHY_TIMING, &config->p_timing); in stm32mp1_ddr_init()
437 set_reg(priv, REGPHY_CAL, &config->p_cal); in stm32mp1_ddr_init()
|
| /external/libunwind/src/ia64/ |
| D | Gparser.c | 155 set_reg (struct ia64_reg_info *reg, enum ia64_where where, int when, in set_reg() function
299 set_reg (sr->curr.reg + unw.save_order[i], IA64_WHERE_GR, in desc_prologue()
328 set_reg (sr->curr.reg + IA64_REG_B1 + i, IA64_WHERE_GR, in desc_br_gr()
343 set_reg (sr->curr.reg + IA64_REG_B1 + i, IA64_WHERE_SPILL_HOME, in desc_br_mem()
361 set_reg (sr->curr.reg + IA64_REG_R4 + i, IA64_WHERE_SPILL_HOME, in desc_frgr_mem()
372 set_reg (sr->curr.reg + base + i, IA64_WHERE_SPILL_HOME, in desc_frgr_mem()
389 set_reg (sr->curr.reg + IA64_REG_F2 + i, IA64_WHERE_SPILL_HOME, in desc_fr_mem()
406 set_reg (sr->curr.reg + IA64_REG_R4 + i, IA64_WHERE_GR, in desc_gr_gr()
421 set_reg (sr->curr.reg + IA64_REG_R4 + i, IA64_WHERE_SPILL_HOME, in desc_gr_mem()
432 set_reg (sr->curr.reg + IA64_REG_PSP, IA64_WHERE_NONE, in desc_mem_stack_f()
[all …]
|
| /external/linux-kselftest/tools/testing/selftests/kvm/include/aarch64/ |
| D | processor.h | 47 static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id, uint64_t val) in set_reg() function
|
| /external/libunwind/scripts/ |
| D | kernel-files.txt | 17 $udir/src/mi/Gset_reg.c $kdir/unwind/set_reg.c
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| D | radeon_uvd.c | 109 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) in set_reg() function
129 set_reg(dec, dec->reg.data0, addr); in send_cmd()
130 set_reg(dec, dec->reg.data1, addr >> 32); in send_cmd()
133 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off); in send_cmd()
134 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4); in send_cmd()
136 set_reg(dec, dec->reg.cmd, cmd << 1); in send_cmd()
1260 set_reg(dec, dec->reg.cntl, 1); in ruvd_end_frame()
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_uvd.c | 105 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) in set_reg() function
125 set_reg(dec, dec->reg.data0, addr); in send_cmd()
126 set_reg(dec, dec->reg.data1, addr >> 32); in send_cmd()
129 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off); in send_cmd()
130 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4); in send_cmd()
132 set_reg(dec, dec->reg.cmd, cmd << 1); in send_cmd()
1346 set_reg(dec, dec->reg.cntl, 1); in ruvd_end_frame()
|
| D | radeon_vcn_dec.c | 780 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val) in set_reg() function
798 set_reg(dec, RDECODE_GPCOM_VCPU_DATA0, addr); in send_cmd()
799 set_reg(dec, RDECODE_GPCOM_VCPU_DATA1, addr >> 32); in send_cmd()
800 set_reg(dec, RDECODE_GPCOM_VCPU_CMD, cmd << 1); in send_cmd()
1182 set_reg(dec, RDECODE_ENGINE_CNTL, 1); in radeon_dec_end_frame()
|
| /external/libunwind/include/ |
| D | libunwind-common.h | 253 #define unw_set_reg UNW_OBJ(set_reg)
|
| D | libunwind-common.h.in | 220 #define unw_set_reg UNW_OBJ(set_reg)
|
| /external/v8/src/arm64/ |
| D | simulator-arm64.h | 821 void set_reg(unsigned code, T value,
830 set_reg(code, value, r31mode);
835 set_reg(code, value, r31mode);
862 set_reg(kLinkRegCode, value); in set_lr()
868 set_reg(31, value, Reg31IsStackPointer); in set_sp()
|
| D | simulator-arm64.cc | 827 set_reg<T>(instr->Rd(), new_val); in AddSubWithCarry()
902 set_reg<T>(instr->Rd(), result); in Extract()
1436 set_reg(instr->Rd(), instr->ImmPCOffsetTarget()); in VisitPCRelAddressing()
1548 set_reg<T>(instr->Rd(), new_val, instr->RdMode()); in AddSubHelper()
1648 set_reg<T>(instr->Rd(), result, instr->RdMode()); in LogicalHelper()
2072 set_reg(addr_reg, address + offset, Reg31IsStackPointer); in LoadStoreWriteBack()
2379 set_reg<T>(instr->Rd(), result); in DataProcessing2Source()
2501 set_reg<T>(instr->Rd(), result); in BitfieldHelper()
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 881 void set_reg(unsigned code,
945 void set_reg(unsigned size,
|