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Searched refs:setcc (Results 1 – 25 of 113) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrFPU.td140 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
149 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
153 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
157 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
160 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
163 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
166 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE),
169 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT),
[all …]
DMBlazeInstrInfo.td754 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ),
757 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE),
760 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT),
763 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT),
766 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE),
769 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE),
772 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT),
775 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT),
778 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE),
781 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dv_cndmask.ll16 %setcc = icmp ne i32 %c, 0
17 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
34 %setcc = icmp ne i32 %c, 0
35 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
54 %setcc = fcmp one float %x, 0.0
55 %select = select i1 %setcc, float 1.0, float %z
69 %setcc = fcmp one float %x, 0.0
70 %select = select i1 %setcc, float 1.0, float %x
84 %setcc = fcmp one float %x, 0.0
85 %select = select i1 %setcc, float 0.0, float %z
[all …]
Dlegalizedag-bug-expand-setcc.ll5 ; setcc to select_cc.
/external/llvm/test/CodeGen/AMDGPU/
Dv_cndmask.ll15 %setcc = icmp ne i32 %c, 0
16 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
32 %setcc = icmp ne i32 %c, 0
33 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
Dsetcc.ll379 ; Make sure we don't try to emit i1 setcc ops
380 ; FUNC-LABEL: setcc-i1
383 define void @setcc-i1(i32 %in) {
393 ; FUNC-LABEL: setcc-i1-and-xor
397 define void @setcc-i1-and-xor(i32 addrspace(1)* %out, float %cond) #0 {
Dlegalizedag-bug-expand-setcc.ll5 ; setcc to select_cc.
/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td451 (setcc v4f64:$FRA, v4f64:$FRB, SETUO))]>;
456 (setcc v4f32:$FRA, v4f32:$FRB, SETUO))]>;
462 (setcc v4f64:$FRA, v4f64:$FRB, SETOLT))]>;
467 (setcc v4f32:$FRA, v4f32:$FRB, SETOLT))]>;
473 (setcc v4f64:$FRA, v4f64:$FRB, SETOGT))]>;
478 (setcc v4f32:$FRA, v4f32:$FRB, SETOGT))]>;
484 (setcc v4f64:$FRA, v4f64:$FRB, SETOEQ))]>;
489 (setcc v4f32:$FRA, v4f32:$FRB, SETOEQ))]>;
992 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOGE),
995 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOLE),
[all …]
DPPCInstrInfo.td2930 // match setcc on i1 variables.
2948 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2950 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2969 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2971 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2974 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2988 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2990 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3004 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3006 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td451 (setcc v4f64:$FRA, v4f64:$FRB, SETUO))]>;
456 (setcc v4f32:$FRA, v4f32:$FRB, SETUO))]>;
462 (setcc v4f64:$FRA, v4f64:$FRB, SETOLT))]>;
467 (setcc v4f32:$FRA, v4f32:$FRB, SETOLT))]>;
473 (setcc v4f64:$FRA, v4f64:$FRB, SETOGT))]>;
478 (setcc v4f32:$FRA, v4f32:$FRB, SETOGT))]>;
484 (setcc v4f64:$FRA, v4f64:$FRB, SETOEQ))]>;
489 (setcc v4f32:$FRA, v4f32:$FRB, SETOEQ))]>;
992 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOGE),
995 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOLE),
[all …]
DPPCInstrInfo.td3214 // match setcc on i1 variables.
3232 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3234 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3253 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
3255 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3258 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3272 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3274 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3288 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3290 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dpr28504.ll4 ; We have a sext(setcc x, y, cc) -> (select (setcc x, y, cc), T, 0) combine,
5 ; BUT this combine is only triggered post-legalization, so the setcc's return
Dpr35399.ll4 ; Make sure we emit opoosite setcc instructions.
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFormats.td66 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
69 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
74 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
77 [(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))],
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetSelectionDAG.td144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
395 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
768 // setcc convenience fragments.
770 (setcc node:$lhs, node:$rhs, SETOEQ)>;
772 (setcc node:$lhs, node:$rhs, SETOGT)>;
774 (setcc node:$lhs, node:$rhs, SETOGE)>;
776 (setcc node:$lhs, node:$rhs, SETOLT)>;
778 (setcc node:$lhs, node:$rhs, SETOLE)>;
780 (setcc node:$lhs, node:$rhs, SETONE)>;
782 (setcc node:$lhs, node:$rhs, SETO)>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXInstrInfo.td282 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
286 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
292 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
297 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
303 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
308 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
313 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
318 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
325 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp),
331 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
[all …]
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td164 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
466 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
971 // setcc convenience fragments.
973 (setcc node:$lhs, node:$rhs, SETOEQ)>;
975 (setcc node:$lhs, node:$rhs, SETOGT)>;
977 (setcc node:$lhs, node:$rhs, SETOGE)>;
979 (setcc node:$lhs, node:$rhs, SETOLT)>;
981 (setcc node:$lhs, node:$rhs, SETOLE)>;
983 (setcc node:$lhs, node:$rhs, SETONE)>;
985 (setcc node:$lhs, node:$rhs, SETO)>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td168 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
448 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
1100 // setcc convenience fragments.
1102 (setcc node:$lhs, node:$rhs, SETOEQ)>;
1104 (setcc node:$lhs, node:$rhs, SETOGT)>;
1106 (setcc node:$lhs, node:$rhs, SETOGE)>;
1108 (setcc node:$lhs, node:$rhs, SETOLT)>;
1110 (setcc node:$lhs, node:$rhs, SETOLE)>;
1112 (setcc node:$lhs, node:$rhs, SETONE)>;
1114 (setcc node:$lhs, node:$rhs, SETO)>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFormats.td150 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
154 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
160 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
164 [(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))],
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc1414 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:…
1430 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:…
1460 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 42…
1476 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 42…
1511 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64]…
1527 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64]…
1558 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:…
1574 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:…
1604 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } i64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Pre…
1627 …// Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } i64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Pre…
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td948 // setcc convenience fragments.
950 (setcc node:$lhs, node:$rhs, SETOEQ)>;
952 (setcc node:$lhs, node:$rhs, SETOGT)>;
954 (setcc node:$lhs, node:$rhs, SETOGE)>;
956 (setcc node:$lhs, node:$rhs, SETOLT)>;
958 (setcc node:$lhs, node:$rhs, SETOLE)>;
960 (setcc node:$lhs, node:$rhs, SETONE)>;
962 (setcc node:$lhs, node:$rhs, SETO)>;
964 (setcc node:$lhs, node:$rhs, SETUO)>;
966 (setcc node:$lhs, node:$rhs, SETUEQ)>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPU64InstrInfo.td18 // 3. i64 setcc results are i32, which are subsequently converted to a FSM
21 // 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
48 // setcc the negative condition:
64 // i64 seteq (equality): the setcc result is i32, which is converted to a
67 // v2i64 seteq (equality): the setcc result is v4i32
/external/llvm/test/CodeGen/Mips/
Dsitofp-selectcc-opt.ll8 ; (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dsitofp-selectcc-opt.ll8 ; (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
/external/llvm/test/Transforms/LoopStrengthReduce/
Dexit_compare_live_range.ll2 ; having overlapping live ranges that result in copies. We want the setcc

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