1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Board specific setup info 4 * 5 * (C) Copyright 2004, ARM Ltd. 6 * Philippe Robin, <philippe.robin@arm.com> 7 */ 8 9#include <config.h> 10 11 /* Reset using CM control register */ 12.global reset_cpu 13reset_cpu: 14 mov r0, #CM_BASE 15 ldr r1,[r0,#OS_CTRL] 16 orr r1,r1,#CMMASK_RESET 17 str r1,[r0,#OS_CTRL] 18 19reset_failed: 20 b reset_failed 21 22/* Set up the platform, once the cpu has been initialized */ 23.globl lowlevel_init 24lowlevel_init: 25 /* If U-Boot has been run after the ARM boot monitor 26 * then all the necessary actions have been done 27 * otherwise we are running from user flash mapped to 0x00000000 28 * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED -- 29 * Changes to the (possibly soft) reset defaults of the processor 30 * itself should be performed in cpu/arm<>/start.S 31 * This function affects only the core module or board settings 32 */ 33 34#ifdef CONFIG_CM_INIT 35 /* CM has an initialization register 36 * - bits in it are wired into test-chip pins to force 37 * reset defaults 38 * - may need to change its contents for U-Boot 39 */ 40 41 /* set the desired CM specific value */ 42 mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */ 43 44#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) 45 orr r2,r2,#CMMASK_INIT_102 46#else 47 48#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ 49 !defined (CONFIG_CM940T) 50 51#ifdef CONFIG_CM_MULTIPLE_SSRAM 52 /* set simple mapping */ 53 and r2,r2,#CMMASK_MAP_SIMPLE 54#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ 55 56#ifdef CONFIG_CM_TCRAM 57 /* disable TCRAM */ 58 and r2,r2,#CMMASK_TCRAM_DISABLE 59#endif /* #ifdef CONFIG_CM_TCRAM */ 60 61#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ 62 defined (CONFIG_CM1136JF_S) 63 64 and r2,r2,#CMMASK_LE 65 66#endif /* cpu with little endian initialization */ 67 68 orr r2,r2,#CMMASK_CMxx6_COMMON 69 70#endif /* CMxx6 code */ 71 72#endif /* ARM102xxE value */ 73 74 /* read CM_INIT */ 75 mov r0, #CM_BASE 76 ldr r1, [r0, #OS_INIT] 77 /* check against desired bit setting */ 78 and r3,r1,r2 79 cmp r3,r2 80 beq init_reg_OK 81 82 /* lock for change */ 83 mov r3, #CMVAL_LOCK1 84 add r3,r3,#CMVAL_LOCK2 85 str r3, [r0, #OS_LOCK] 86 /* set desired value */ 87 orr r1,r1,r2 88 /* write & relock CM_INIT */ 89 str r1, [r0, #OS_INIT] 90 mov r1, #CMVAL_UNLOCK 91 str r1, [r0, #OS_LOCK] 92 93 /* soft reset so new values used */ 94 b reset_cpu 95 96init_reg_OK: 97 98#endif /* CONFIG_CM_INIT */ 99 100 mov pc, lr 101 102#ifdef CONFIG_CM_SPD_DETECT 103 /* Fast memory is available for the DRAM data 104 * - ensure it has been transferred, then summarize the data 105 * into a CM register 106 */ 107.globl dram_query 108dram_query: 109 stmfd r13!,{r4-r6,lr} 110 /* set up SDRAM info */ 111 /* - based on example code from the CM User Guide */ 112 mov r0, #CM_BASE 113 114readspdbit: 115 ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ 116 and r1, r1, #0x20 /* mask SPD bit (5) */ 117 cmp r1, #0x20 /* test if set */ 118 bne readspdbit 119 120setupsdram: 121 add r0, r0, #OS_SPD /* address the copy of the SDP data */ 122 ldrb r1, [r0, #3] /* number of row address lines */ 123 ldrb r2, [r0, #4] /* number of column address lines */ 124 ldrb r3, [r0, #5] /* number of banks */ 125 ldrb r4, [r0, #31] /* module bank density */ 126 mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ 127 mov r5, r5, ASL#2 /* size in MB */ 128 mov r0, #CM_BASE /* reload for later code */ 129 cmp r5, #0x10 /* is it 16MB? */ 130 bne not16 131 mov r6, #0x2 /* store size and CAS latency of 2 */ 132 b writesize 133 134not16: 135 cmp r5, #0x20 /* is it 32MB? */ 136 bne not32 137 mov r6, #0x6 138 b writesize 139 140not32: 141 cmp r5, #0x40 /* is it 64MB? */ 142 bne not64 143 mov r6, #0xa 144 b writesize 145 146not64: 147 cmp r5, #0x80 /* is it 128MB? */ 148 bne not128 149 mov r6, #0xe 150 b writesize 151 152not128: 153 /* if it is none of these sizes then it is either 256MB, or 154 * there is no SDRAM fitted so default to 256MB 155 */ 156 mov r6, #0x12 157 158writesize: 159 mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */ 160 orr r2, r1, r2, ASL#12 /* OR in column address lines */ 161 orr r3, r2, r3, ASL#16 /* OR in number of banks */ 162 orr r6, r6, r3 /* OR in size and CAS latency */ 163 str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */ 164 165#endif /* #ifdef CONFIG_CM_SPD_DETECT */ 166 167 ldmfd r13!,{r4-r6,pc} /* back to caller */ 168 169#ifdef CONFIG_CM_REMAP 170 /* CM remap bit is operational 171 * - use it to map writeable memory at 0x00000000, in place of flash 172 */ 173.globl cm_remap 174cm_remap: 175 stmfd r13!,{r4-r10,lr} 176 177 mov r0, #CM_BASE 178 ldr r1, [r0, #OS_CTRL] 179 orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ 180 str r1, [r0, #OS_CTRL] 181 182 /* Now 0x00000000 is writeable, replace the vectors */ 183 ldr r0, =_start /* r0 <- start of vectors */ 184 add r2, r0, #64 /* r2 <- past vectors */ 185 sub r1,r1,r1 /* destination 0x00000000 */ 186 187copy_vec: 188 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 189 stmia r1!, {r3-r10} /* copy to target address [r1] */ 190 cmp r0, r2 /* until source end address [r2] */ 191 ble copy_vec 192 193 ldmfd r13!,{r4-r10,pc} /* back to caller */ 194 195#endif /* #ifdef CONFIG_CM_REMAP */ 196