• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * UniPhier SG (SoC Glue) block registers
4  *
5  * Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
6  * Copyright (C) 2016-2017 Socionext Inc.
7  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8  */
9 
10 #ifndef UNIPHIER_SG_REGS_H
11 #define UNIPHIER_SG_REGS_H
12 
13 /* Base Address */
14 #define SG_CTRL_BASE			0x5f800000
15 #define SG_DBG_BASE			0x5f900000
16 
17 /* Revision */
18 #define SG_REVISION			(SG_CTRL_BASE | 0x0000)
19 
20 /* Memory Configuration */
21 #define SG_MEMCONF			(SG_CTRL_BASE | 0x0400)
22 
23 #define SG_MEMCONF_CH0_SZ_MASK		((0x1 << 10) | (0x03 << 0))
24 #define SG_MEMCONF_CH0_SZ_64M		((0x0 << 10) | (0x01 << 0))
25 #define SG_MEMCONF_CH0_SZ_128M		((0x0 << 10) | (0x02 << 0))
26 #define SG_MEMCONF_CH0_SZ_256M		((0x0 << 10) | (0x03 << 0))
27 #define SG_MEMCONF_CH0_SZ_512M		((0x1 << 10) | (0x00 << 0))
28 #define SG_MEMCONF_CH0_SZ_1G		((0x1 << 10) | (0x01 << 0))
29 #define SG_MEMCONF_CH0_NUM_MASK		(0x1 << 8)
30 #define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
31 #define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)
32 
33 #define SG_MEMCONF_CH1_SZ_MASK		((0x1 << 11) | (0x03 << 2))
34 #define SG_MEMCONF_CH1_SZ_64M		((0x0 << 11) | (0x01 << 2))
35 #define SG_MEMCONF_CH1_SZ_128M		((0x0 << 11) | (0x02 << 2))
36 #define SG_MEMCONF_CH1_SZ_256M		((0x0 << 11) | (0x03 << 2))
37 #define SG_MEMCONF_CH1_SZ_512M		((0x1 << 11) | (0x00 << 2))
38 #define SG_MEMCONF_CH1_SZ_1G		((0x1 << 11) | (0x01 << 2))
39 #define SG_MEMCONF_CH1_NUM_MASK		(0x1 << 9)
40 #define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
41 #define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)
42 
43 #define SG_MEMCONF_CH2_SZ_MASK		((0x1 << 26) | (0x03 << 16))
44 #define SG_MEMCONF_CH2_SZ_64M		((0x0 << 26) | (0x01 << 16))
45 #define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
46 #define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
47 #define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
48 #define SG_MEMCONF_CH2_SZ_1G		((0x1 << 26) | (0x01 << 16))
49 #define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
50 #define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
51 #define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
52 /* PH1-LD6b, ProXstream2, PH1-LD20 only */
53 #define SG_MEMCONF_CH2_DISABLE		(0x1 << 21)
54 
55 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
56 
57 #define SG_USBPHYCTRL			(SG_CTRL_BASE | 0x500)
58 #define SG_ETPHYPSHUT			(SG_CTRL_BASE | 0x554)
59 #define SG_ETPHYCNT			(SG_CTRL_BASE | 0x550)
60 
61 /* Pin Control */
62 #define SG_PINCTRL_BASE			(SG_CTRL_BASE | 0x1000)
63 
64 /* PH1-Pro4, PH1-Pro5 */
65 #define SG_LOADPINCTRL			(SG_CTRL_BASE | 0x1700)
66 
67 /* Input Enable */
68 #define SG_IECTRL			(SG_CTRL_BASE | 0x1d00)
69 
70 /* Pin Monitor */
71 #define SG_PINMON0			(SG_DBG_BASE | 0x0100)
72 #define SG_PINMON2			(SG_DBG_BASE | 0x0108)
73 
74 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK	(0x3 << 19)
75 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT	(0x0 << 19)
76 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A	(0x2 << 19)
77 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B	(0x3 << 19)
78 
79 #define SG_PINMON0_CLK_MODE_AXOSEL_MASK		(0x3 << 16)
80 #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ	(0x0 << 16)
81 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ	(0x1 << 16)
82 #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ	(0x2 << 16)
83 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ	(0x3 << 16)
84 
85 #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT	(0x0 << 16)
86 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U	(0x1 << 16)
87 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ	(0x2 << 16)
88 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A	(0x3 << 16)
89 
90 #ifdef __ASSEMBLY__
91 
92 	.macro	sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
93 	ldr	\ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
94 	ldr	\rd, [\ra]
95 	and	\rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
96 	orr	\rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
97 	str	\rd, [\ra]
98 	.endm
99 
100 #else
101 
102 #include <linux/types.h>
103 #include <linux/io.h>
104 
sg_set_pinsel(unsigned pin,unsigned muxval,unsigned mux_bits,unsigned reg_stride)105 static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
106 				 unsigned mux_bits, unsigned reg_stride)
107 {
108 	unsigned shift = pin * mux_bits % 32;
109 	unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
110 	u32 mask = (1U << mux_bits) - 1;
111 	u32 tmp;
112 
113 	tmp = readl(reg);
114 	tmp &= ~(mask << shift);
115 	tmp |= (mask & muxval) << shift;
116 	writel(tmp, reg);
117 }
118 
sg_set_iectrl(unsigned pin)119 static inline void sg_set_iectrl(unsigned pin)
120 {
121 	unsigned bit = pin % 32;
122 	unsigned long reg = SG_IECTRL + pin / 32 * 4;
123 	u32 tmp;
124 
125 	tmp = readl(reg);
126 	tmp |= 1 << bit;
127 	writel(tmp, reg);
128 }
129 
sg_set_iectrl_range(unsigned min,unsigned max)130 static inline void sg_set_iectrl_range(unsigned min, unsigned max)
131 {
132 	int i;
133 
134 	for (i = min; i <= max; i++)
135 		sg_set_iectrl(i);
136 }
137 
138 #endif /* __ASSEMBLY__ */
139 
140 #endif /* UNIPHIER_SG_REGS_H */
141