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Searched refs:sgpr_idx (Results 1 – 4 of 4) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_cmd_buffer.c583 if (loc->sgpr_idx == -1) in radv_emit_userdata_address()
587 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2); in radv_emit_userdata_address()
611 if (loc->sgpr_idx == -1) in radv_update_multisample_state()
633 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset); in radv_update_multisample_state()
874 if (loc->sgpr_idx != -1) { in radv_emit_tess_shaders()
878 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4); in radv_emit_tess_shaders()
887 if (loc->sgpr_idx != -1) { in radv_emit_tess_shaders()
892 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, in radv_emit_tess_shaders()
897 if (loc->sgpr_idx != -1) { in radv_emit_tess_shaders()
902 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, in radv_emit_tess_shaders()
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Dradv_pipeline.c2695 if (loc->sgpr_idx != -1) { in radv_pipeline_init()
2697 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4; in radv_pipeline_init()
/external/mesa3d/src/amd/common/
Dac_nir_to_llvm.h92 int8_t sgpr_idx; member
Dac_nir_to_llvm.c508 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs, in set_loc() argument
511 ud_info->sgpr_idx = *sgpr_idx; in set_loc()
515 *sgpr_idx += num_sgprs; in set_loc()
519 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx, in set_loc_shader() argument
526 set_loc(ud_info, sgpr_idx, num_sgprs, 0); in set_loc_shader()
530 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx, in set_loc_desc() argument
537 set_loc(ud_info, sgpr_idx, 2, indirect_offset); in set_loc_desc()
6839 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1; in ac_translate_nir_to_llvm()
6841 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1; in ac_translate_nir_to_llvm()