Searched refs:shifted_reg (Results 1 – 2 of 2) sorted by relevance
| /external/v8/src/arm64/ |
| D | simulator-logic-arm64.cc | 1476 LogicVRegister shifted_reg = sshr(vform, temp, src, shift); in ssra() local
1477 return add(vform, dst, dst, shifted_reg); in ssra()
1483 LogicVRegister shifted_reg = ushr(vform, temp, src, shift); in usra() local
1484 return add(vform, dst, dst, shifted_reg); in usra()
1490 LogicVRegister shifted_reg = sshr(vform, temp, src, shift).Round(vform); in srsra() local
1491 return add(vform, dst, dst, shifted_reg); in srsra()
1497 LogicVRegister shifted_reg = ushr(vform, temp, src, shift).Round(vform); in ursra() local
1498 return add(vform, dst, dst, shifted_reg); in ursra()
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| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 1628 LogicVRegister shifted_reg = sshr(vform, temp, src, shift); in ssra() local
1629 return add(vform, dst, dst, shifted_reg); in ssra()
1638 LogicVRegister shifted_reg = ushr(vform, temp, src, shift); in usra() local
1639 return add(vform, dst, dst, shifted_reg); in usra()
1648 LogicVRegister shifted_reg = sshr(vform, temp, src, shift).Round(vform); in srsra() local
1649 return add(vform, dst, dst, shifted_reg); in srsra()
1658 LogicVRegister shifted_reg = ushr(vform, temp, src, shift).Round(vform); in ursra() local
1659 return add(vform, dst, dst, shifted_reg); in ursra()
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