Searched refs:shl1 (Results 1 – 25 of 47) sorted by relevance
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | ashift-left-right.ll | 7 %shl1 = shl i32 16, %a
9 %ret = mul i32 %shl1, %shl2
17 %shl1 = ashr i32 16, %a
19 %ret = mul i32 %shl1, %shl2
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | ashift-left-right.ll | 7 %shl1 = shl i32 16, %a
9 %ret = mul i32 %shl1, %shl2
17 %shl1 = ashr i32 16, %a
19 %ret = mul i32 %shl1, %shl2
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | lds_atomic_f32.ll | 19 %shl1 = shl i32 %idx.add, 4
21 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
40 %shl1 = shl i32 %idx.add, 4
42 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
61 %shl1 = shl i32 %idx.add, 4
63 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
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| D | shl_add_ptr.ll | 292 %shl1 = shl i32 %idx.add, 4
294 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)*
309 %shl1 = shl i32 %idx.add, 4
311 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)*
326 %shl1 = shl i32 %idx.add, 5
328 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)*
344 %shl1 = shl i32 %idx.add, 3
346 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)*
362 %shl1 = shl i32 %idx.add, 4
364 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)*
[all …]
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| D | mul_int24.ll | 77 %shl1.i = shl i32 %b, 8
78 %shr2.i = ashr i32 %shl1.i, 8
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| /external/llvm/test/CodeGen/X86/ |
| D | sse2-vector-shifts.ll | 288 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
289 ret <4 x i32> %shl1
298 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
299 ret <4 x i32> %shl1
309 %shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5>
310 ret <4 x i32> %shl1
344 %shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17>
345 ret <4 x i32> %shl1
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| D | vec_shift4.ll | 5 define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
6 ; X32-LABEL: shl1:
14 ; X64-LABEL: shl1:
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| D | targetLoweringGeneric.ll | 23 %shl1 = shl i32 %xor3, %i32In4
24 %sub1 = sub i32 %or2, %shl1
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| D | legalize-shift-64.ll | 78 %shl1 = shl i64 1, %sh_prom
79 %cmp = icmp ne i64 %shl1, 4294967296
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | sse2-vector-shifts.ll | 288 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
289 ret <4 x i32> %shl1
298 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
299 ret <4 x i32> %shl1
309 %shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5>
310 ret <4 x i32> %shl1
343 %shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17>
344 ret <4 x i32> %shl1
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| D | vec_shift4.ll | 5 define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
6 ; X32-LABEL: shl1:
14 ; X64-LABEL: shl1:
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| D | targetLoweringGeneric.ll | 23 %shl1 = shl i32 %xor3, %i32In4
24 %sub1 = sub i32 %or2, %shl1
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| D | pr22338.ll | 45 %shl1 = shl i32 %sext, %sel1
47 %tobool = icmp eq i32 %shl1, 0
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| D | legalize-shift-64.ll | 165 %shl1 = shl i64 1, %sh_prom
166 %cmp = icmp ne i64 %shl1, 4294967296
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| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | address-mode-opt.ll | 155 %shl1 = shl i32 %arg.int, 2
156 %addr.int = or i32 1, %shl1
168 %shl1 = shl i32 %arg.int, 2
169 %addr.int = or i32 5, %shl1
181 %shl1 = shl i32 %arg.int, 2
182 %addr.int = or i32 -1, %shl1
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | micromips-shift.ll | 18 %shl1 = shl i32 %1, 10
19 store i32 %shl1, i32* @d, align 4
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/loop-idiom/ |
| D | pmpy.ll | 20 %shl1 = shl i64 %conv, %sh_prom
21 %xor = xor i64 %shl1, %R.06
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| /external/llvm/test/CodeGen/Mips/ |
| D | micromips-shift.ll | 18 %shl1 = shl i32 %1, 10
19 store i32 %shl1, i32* @d, align 4
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | ldtoc-inv.ll | 23 %shl1 = shl i32 %0, %step_size
24 %idxprom2 = sext i32 %shl1 to i64
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | ldtoc-inv.ll | 23 %shl1 = shl i32 %0, %step_size
24 %idxprom2 = sext i32 %shl1 to i64
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| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| D | nsw.ll | 31 ; CHECK: @shl1
34 define i64 @shl1(i64 %X, i64* %P) nounwind {
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | nsw.ll | 31 ; CHECK-LABEL: @shl1(
34 define i64 @shl1(i64 %X, i64* %P) nounwind {
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| /external/llvm/test/Transforms/InstCombine/ |
| D | nsw.ll | 31 ; CHECK-LABEL: @shl1(
34 define i64 @shl1(i64 %X, i64* %P) nounwind {
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| D | bswap.ll | 133 %shl1 = and i32 %and2, 65280
134 %or = or i32 %and1, %shl1
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | vec_shift4.ll | 3 define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
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