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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dashift-left-right.ll8 %shl2 = shl i32 %b, 16
9 %ret = mul i32 %shl1, %shl2
18 %shl2 = ashr i32 %b, 16
19 %ret = mul i32 %shl1, %shl2
Dexpand-condsets-extend.ll30 %shl2.i322 = or i64 undef, -9223372036854775808
49 %shr.i263 = lshr i64 %shl2.i322, 32
76 %shl2.i207 = shl i64 %aSig0.3554, 61
77 %or.i209 = or i64 %shl2.i207, 0
Dtail-dup-subreg-map.ll59 %shl2.i = shl i64 %aSig0.2, 15
61 %or.i = or i64 %shl2.i, %shr.i
/external/llvm/test/CodeGen/Hexagon/
Dashift-left-right.ll8 %shl2 = shl i32 %b, 16
9 %ret = mul i32 %shl1, %shl2
18 %shl2 = ashr i32 %b, 16
19 %ret = mul i32 %shl1, %shl2
Dtail-dup-subreg-map.ll59 %shl2.i = shl i64 %aSig0.2, 15
61 %or.i = or i64 %shl2.i, %shr.i
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/X86/
Dpr34545.ll28 %shl2 = shl i32 %shl, %2
29 …tail call void @llvm.dbg.value(metadata i32 %shl2, metadata !18, metadata !DIExpression()), !dbg !…
30 store i32 %shl2, i32* @var
31 ret i32 %shl2
Ddbg-value-transfer-order.ll72 %shl2 = shl i32 %add, 3, !dbg !55
73 %idxprom = zext i32 %shl2 to i64, !dbg !57
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Deon.ll27 %shl2 = shl i64 %xor, %xor1
28 ret i64 %shl2
Darm64-bitfield-extract.ll550 %shl2 = shl nuw nsw i64 %shr47, 2
551 %shl2.trunc = trunc i64 %shl2 to i32
552 %and12 = and i32 %shl2.trunc, 12
/external/llvm/test/CodeGen/AArch64/
Deon.ll27 %shl2 = shl i64 %xor, %xor1
28 ret i64 %shl2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvec_shift4.ll33 define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
34 ; X32-LABEL: shl2:
57 ; X64-LABEL: shl2:
Dpr22338.ll46 %shl2 = shl i32 %sext, %sel2
54 ret i32 %shl2
Dfold-tied-op.ll39 %shl2 = shl i64 %3, 2
41 %or3 = or i64 %shl2, %shr
Dx86-shifts.ll76 define <2 x i64> @shl2(<2 x i64> %A) nounwind {
77 ; X32-LABEL: shl2:
85 ; X64-LABEL: shl2:
Dmmx-coalescing.ll18 %shl2 = shl i32 1, %D
/external/llvm/test/CodeGen/X86/
Dvec_shift4.ll33 define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
34 ; X32-LABEL: shl2:
57 ; X64-LABEL: shl2:
Dfold-tied-op.ll39 %shl2 = shl i64 %3, 2
41 %or3 = or i64 %shl2, %shr
Dx86-shifts.ll42 define <2 x i64> @shl2(<2 x i64> %A) nounwind {
44 ; CHECK: shl2
Dmmx-coalescing.ll18 %shl2 = shl i32 1, %D
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dmips64extins.ll34 %shl2 = shl i64 %j, 8
35 %and = and i64 %shl2, 261888
/external/llvm/test/CodeGen/Mips/
Dmips64extins.ll34 %shl2 = shl i64 %j, 8
35 %and = and i64 %shl2, 261888
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LowerTypeTests/
Dimport.ll138 ; CHECK-NEXT: [[shl2:%.*]] = shl i32 1, [[and]]
139 …86-NEXT: [[and2:%.*]] = and i32 ptrtoint ([0 x i8]* @__typeid_inline5_inline_bits to i32), [[shl2]]
140 ; ARM-NEXT: [[and2:%.*]] = and i32 123, [[shl2]]
166 ; CHECK-NEXT: [[shl2:%.*]] = shl i64 1, [[and]]
167 …86-NEXT: [[and2:%.*]] = and i64 ptrtoint ([0 x i8]* @__typeid_inline6_inline_bits to i64), [[shl2]]
168 ; ARM-NEXT: [[and2:%.*]] = and i64 1000000000000, [[shl2]]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dvec_shift4.ll16 define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
Dx86-shifts.ll39 define <2 x i64> @shl2(<2 x i64> %A) nounwind {
41 ; CHECK: shl2
/external/llvm/test/Transforms/InstCombine/
Dmul.ll255 ; CHECK-NEXT: %[[shl2:.*]] = shl i32 %[[shl1]], %A
256 ; CHECK-NEXT: ret i32 %[[shl2]]

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