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Searched refs:shrn2 (Results 1 – 25 of 43) sorted by relevance

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/external/capstone/suite/MC/AArch64/
Dneon-simd-shift.s.cs95 0x20,0x84,0x0d,0x4f = shrn2 v0.16b, v1.8h, #3
96 0x20,0x84,0x1d,0x4f = shrn2 v0.8h, v1.4s, #3
97 0x20,0x84,0x3d,0x4f = shrn2 v0.4s, v1.2d, #3
/external/llvm/test/CodeGen/AArch64/
Darm64-vecFold.ll10 ; CHECK-NEXT: shrn2.16b v0, v1, #5
26 ; CHECK-NEXT: shrn2.8h v0, v1, #5
42 ; CHECK-NEXT: shrn2.4s v0, v1, #5
71 ; CHECK-NEXT: shrn2.8h v0, v2, #5
Dneon-diagnostics.ll16 ; CHECK-NOT: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #35
Darm64-neon-simd-shift.ll263 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
275 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
287 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
299 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
311 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
323 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
Darm64-vshift.ll706 ;CHECK: shrn2.16b v0, {{v[0-9]+}}, #1
717 ;CHECK: shrn2.8h v0, {{v[0-9]+}}, #1
728 ;CHECK: shrn2.4s v0, {{v[0-9]+}}, #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vecFold.ll10 ; CHECK-NEXT: shrn2.16b v0, v1, #5
26 ; CHECK-NEXT: shrn2.8h v0, v1, #5
42 ; CHECK-NEXT: shrn2.4s v0, v1, #5
71 ; CHECK-NEXT: shrn2.8h v0, v2, #5
Dneon-diagnostics.ll16 ; CHECK-NOT: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #35
Darm64-neon-simd-shift.ll263 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
275 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
287 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
299 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
311 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
323 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
Darm64-vshift.ll706 ;CHECK: shrn2.16b v0, {{v[0-9]+}}, #1
717 ;CHECK: shrn2.8h v0, {{v[0-9]+}}, #1
728 ;CHECK: shrn2.4s v0, {{v[0-9]+}}, #1
/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s265 shrn2 v0.16b, v1.8h, #3
266 shrn2 v0.8h, v1.4s, #3
267 shrn2 v0.4s, v1.2d, #3
Darm64-advsimd.s1474 shrn2.16b v0, v0, #2
1476 shrn2.8h v0, v0, #4
1478 shrn2.4s v0, v0, #6
1646 ; CHECK: shrn2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x4f]
1648 ; CHECK: shrn2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x4f]
1650 ; CHECK: shrn2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x4f]
1806 shrn2 v8.16b, v9.8h, #2
1808 shrn2 v6.8h, v7.4s, #4
1810 shrn2 v4.4s, v5.2d, #6
1876 ; CHECK: shrn2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x4f]
[all …]
Dneon-diagnostics.s1810 shrn2 v0.16b, v1.8h, #17
1811 shrn2 v0.8h, v1.4s, #33
1812 shrn2 v0.4s, v1.2d, #65
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-simd-shift.s265 shrn2 v0.16b, v1.8h, #3
266 shrn2 v0.8h, v1.4s, #3
267 shrn2 v0.4s, v1.2d, #3
Darm64-advsimd.s1474 shrn2.16b v0, v0, #2
1476 shrn2.8h v0, v0, #4
1478 shrn2.4s v0, v0, #6
1646 ; CHECK: shrn2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x4f]
1648 ; CHECK: shrn2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x4f]
1650 ; CHECK: shrn2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x4f]
1806 shrn2 v8.16b, v9.8h, #2
1808 shrn2 v6.8h, v7.4s, #4
1810 shrn2 v4.4s, v5.2d, #6
1876 ; CHECK: shrn2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x4f]
[all …]
Dneon-diagnostics.s1815 shrn2 v0.16b, v1.8h, #17
1816 shrn2 v0.8h, v1.4s, #33
1817 shrn2 v0.4s, v1.2d, #65
/external/libjpeg-turbo/simd/arm64/
Djsimd_neon.S593 …shrn2 v2.8h, v19.4s, #16 /* wsptr[DCTSIZE*0] = (int)DESCALE(tmp10 + tmp3, CONST_BITS+PA…
594 …shrn2 v9.8h, v21.4s, #16 /* wsptr[DCTSIZE*7] = (int)DESCALE(tmp10 - tmp3, CONST_BITS+PA…
595 …shrn2 v3.8h, v23.4s, #16 /* wsptr[DCTSIZE*1] = (int)DESCALE(tmp11 + tmp2, CONST_BITS+PA…
596 …shrn2 v8.8h, v25.4s, #16 /* wsptr[DCTSIZE*6] = (int)DESCALE(tmp11 - tmp2, CONST_BITS+PA…
597 …shrn2 v4.8h, v27.4s, #16 /* wsptr[DCTSIZE*2] = (int)DESCALE(tmp12 + tmp1, CONST_BITS+PA…
598 …shrn2 v7.8h, v29.4s, #16 /* wsptr[DCTSIZE*5] = (int)DESCALE(tmp12 - tmp1, CONST_BITS+PA…
599 …shrn2 v5.8h, v15.4s, #16 /* wsptr[DCTSIZE*3] = (int)DESCALE(tmp13 + tmp0, CONST_BITS+PA…
600 …shrn2 v6.8h, v17.4s, #16 /* wsptr[DCTSIZE*4] = (int)DESCALE(tmp13 - tmp0, CONST_BITS+PA…
2121 shrn2 v22.8h, v26.4s, #16
2122 shrn2 v24.8h, v30.4s, #16
[all …]
/external/libavc/common/armv8/
Dih264_resi_trans_quant_av8.s525 shrn2 v0.8h, v23.4s, #1 //i4_value = (x3 + x2) >> 1;
527 shrn2 v1.8h, v25.4s, #1 //i4_value = (x3 - x2) >> 1;
/external/v8/src/arm64/
Dsimulator-logic-arm64.cc2118 LogicVRegister Simulator::shrn2(VectorFormat vform, LogicVRegister dst, in shrn2() function in v8::internal::Simulator
2237 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn2()
2769 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in addhn2()
2805 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in subhn2()
Dmacro-assembler-arm64.h1049 V(shrn2, Shrn2) \
Dsimulator-arm64.h1796 LogicVRegister shrn2(VectorFormat vform, LogicVRegister dst,
/external/vixl/src/aarch64/
Dlogic-aarch64.cc2583 LogicVRegister Simulator::shrn2(VectorFormat vform, in shrn2() function in vixl::aarch64::Simulator
2734 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn2()
3492 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in addhn2()
3536 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in subhn2()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2049 # CHECK: shrn2.16b v0, v0, #0x6
2051 # CHECK: shrn2.8h v0, v0, #0xc
2053 # CHECK: shrn2.4s v0, v0, #0x1a
Dneon-instructions.txt957 # CHECK: shrn2 v0.16b, v1.8h, #3
958 # CHECK: shrn2 v0.8h, v1.4s, #3
959 # CHECK: shrn2 v0.4s, v1.2d, #3
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2049 # CHECK: shrn2.16b v0, v0, #0x6
2051 # CHECK: shrn2.8h v0, v0, #0xc
2053 # CHECK: shrn2.4s v0, v0, #0x1a
Dneon-instructions.txt957 # CHECK: shrn2 v0.16b, v1.8h, #3
958 # CHECK: shrn2 v0.8h, v1.4s, #3
959 # CHECK: shrn2 v0.4s, v1.2d, #3

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