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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td548 bits<16> simm16;
555 let Inst{15-0} = simm16;
564 let Inst{15-0} = simm16;
579 (ins s16imm:$simm16),
580 "$sdst, $simm16",
587 (ins SReg_32:$sdst, s16imm:$simm16),
588 (ins SReg_32:$sdst, u16imm:$simm16)),
589 "$sdst, $simm16", []>,
597 (ins SReg_32:$src0, s16imm:$simm16),
598 "$sdst, $simm16",
[all …]
DGCNHazardRecognizer.cpp105 AMDGPU::OpName::simm16); in getHWReg()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrInfo.td84 def simm16 : Operand<i32>;
103 let MIOperandInfo = (ops GPR, simm16);
147 def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt),
151 (ins uimm16:$amt1, simm16:$amt2),
413 def ADDIK : ArithI<0x0C, "addik ", add, simm16, immSExt16>;
414 def RSUBIK : ArithRI<0x0D, "rsubik ", sub, simm16, immSExt16>;
421 def ADDI : ArithI<0x08, "addi ", addc, simm16, immSExt16>;
422 def RSUBI : ArithRI<0x09, "rsubi ", subc, simm16, immSExt16>;
425 def ADDIC : ArithI<0x0A, "addic ", adde, simm16, immSExt16>;
426 def RSUBIC : ArithRI<0x0B, "rsubic ", sube, simm16, immSExt16>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.getreg.ll7 define amdgpu_kernel void @s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds size.
17 define amdgpu_kernel void @readnone_s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds …
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td399 (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16"
405 (ins hwreg:$simm16), " $sdst, $simm16"
411 (ins SReg_32:$sdst, hwreg:$simm16), " $simm16, $sdst"
417 (ins i32imm:$imm, hwreg:$simm16), " $simm16, $imm"
424 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
430 let simm16 = 0;
438 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
439 [(br bb:$simm16)]> {
445 0x00000004, (ins sopp_brtarget:$simm16),
446 "s_cbranch_scc0 $simm16"
[all …]
DSIInstrFormats.td215 bits <16> simm16;
217 let Inst{15-0} = simm16;
225 bits <16> simm16;
228 let Inst{15-0} = simm16;
237 bits <16> simm16;
239 let Inst{15-0} = simm16;
DSIInstrInfo.td929 def "" : SOPK_Pseudo <opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
932 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
933 opName#" $sdst, $simm16">;
935 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
936 opName#" $sdst, $simm16">;
947 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
952 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
958 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
959 " $sdst, $simm16"
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/
DNios2InstrInfo.td25 def simm16 : Operand<i32> {
98 defm ADDI : ArithLogicRegImm16<0x04, "addi", add, simm16, immSExt16>;
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.getreg.ll7 define void @s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds size.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips16InstrInfo.td24 let MIOperandInfo = (ops CPU16Regs, simm16);
36 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
42 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
65 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
83 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
97 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
106 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
122 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
161 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
194 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
[all …]
DMipsInstrInfo.td946 // Like uimm16_64 but coerces simm16 to uimm16.
967 // Like uimm16_64 but coerces simm16 to uimm16.
1047 // Like simm16 but coerces uimm16 to simm16.
1159 let MIOperandInfo = (ops ptr_rc, simm16);
1211 let MIOperandInfo = (ops ptr_rc, simm16);
1222 let MIOperandInfo = (ops ptr_rc, simm16);
1711 InstSE<(outs), (ins RO:$rs, simm16:$imm16),
2037 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
2039 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
2524 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
[all …]
DMicroMipsInstrInfo.td142 let MIOperandInfo = (ops ptr_rc, simm16);
735 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
737 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
739 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
741 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
DMicroMips32r6InstrInfo.td343 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
537 dag InOperandList = (ins simm16:$imm);
DMips32r6InstrInfo.td345 dag InOperandList = (ins simm16:$imm);
/external/llvm/lib/Target/Mips/
DMips16InstrInfo.td24 let MIOperandInfo = (ops CPU16Regs, simm16);
36 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
42 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
65 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
83 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
97 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
106 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
122 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
161 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
194 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
[all …]
DMipsInstrInfo.td741 // Like uimm16_64 but coerces simm16 to uimm16.
762 // Like uimm16_64 but coerces simm16 to uimm16.
837 // Like simm16 but coerces uimm16 to simm16.
936 let MIOperandInfo = (ops ptr_rc, simm16);
988 let MIOperandInfo = (ops ptr_rc, simm16);
995 let MIOperandInfo = (ops ptr_rc, simm16);
1424 InstSE<(outs), (ins RO:$rs, simm16:$imm16),
1689 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1691 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
2137 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
[all …]
DMicroMipsInstrInfo.td129 let MIOperandInfo = (ops ptr_rc, simm16);
678 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
680 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
682 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
684 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1105 (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1107 (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
DMicroMips64r6InstrInfo.td80 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
89 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
DMips32r6InstrInfo.td306 dag InOperandList = (ins simm16:$imm);
319 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
DMicroMips32r6InstrInfo.td337 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
520 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
532 dag InOperandList = (ins simm16:$imm);
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrInfo.td143 def simm16 : Operand<i32>;
155 let MIOperandInfo = (ops CPURegs, simm16);
166 let MIOperandInfo = (ops CPURegs, simm16);
650 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
651 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
652 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
653 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
/external/mesa3d/src/amd/common/
Dac_llvm_build.h322 void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned simm16);
Dac_llvm_build.c1548 void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned simm16) in ac_build_waitcnt() argument
1551 LLVMConstInt(ctx->i32, simm16, false), in ac_build_waitcnt()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dinlineasm-operand-code.ll36 ; This is _also_ -3 because uimm16 values are silently coerced to simm16 when
/external/llvm/test/CodeGen/Mips/
Dinlineasm-operand-code.ll36 ; This is _also_ -3 because uimm16 values are silently coerced to simm16 when

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