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Searched refs:sirccsr (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-mx7ulp/
Dscg.h278 u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */ member
/external/u-boot/arch/arm/mach-imx/mx7ulp/
Dscg.c34 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
74 reg = readl(&scg1_regs->sirccsr); in scg_sircdiv_get_rate()