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/external/llvm/test/MC/AMDGPU/
Dmubuf.s33 buffer_load_dword v1, off, s[4:7], s1 offset:4 slc
45 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
49 buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe
69 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc
81 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe
85 buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe
105 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc
117 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe
121 buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe
141 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc
[all …]
Dflat.s28 flat_load_dword v1, v[3:4] glc slc
38 flat_load_dword v1, v[3:4] glc slc tfe
43 flat_load_dword v1, v[3:4] slc
48 flat_load_dword v1, v[3:4] slc tfe
66 flat_store_dword v[3:4], v1 glc slc
74 flat_store_dword v[3:4], v1 glc slc tfe
78 flat_store_dword v[3:4], v1 slc
82 flat_store_dword v[3:4], v1 slc tfe
100 flat_atomic_add v1 v[3:4], v5 glc slc
110 flat_atomic_add v1 v[3:4], v5 glc slc tfe
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dmubuf.s33 buffer_load_dword v1, off, s[4:7], s1 offset:4 slc
45 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
49 buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe
69 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc
81 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe
85 buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe
105 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc
117 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe
121 buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe
141 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc
[all …]
Dflat-gfx9.s26 flat_load_dword v1, v[3:4] offset:4 glc slc
30 flat_atomic_add v[3:4], v5 offset:8 slc
34 flat_atomic_add v[3:4], v5 inst_offset:8 slc
42 flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 slc
50 flat_atomic_cmpswap v[1:2], v[3:4] slc
64 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc slc
72 flat_atomic_cmpswap v0, v[1:2], v[3:4] glc slc
83 flat_atomic_cmpswap v0, v[1:2], v[3:4] slc
Dflat.s28 flat_load_dword v1, v[3:4] glc slc
41 flat_store_dword v[3:4], v1 glc slc
46 flat_store_dword v[3:4], v1 slc
55 flat_atomic_add v1, v[3:4], v5 offset:0 glc slc
60 flat_atomic_add v[3:4], v5 slc
Dmimg.s39 image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16
72 image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16
179 image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc tfe lwe da
208 image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm glc slc lwe da
302 image_atomic_add v8, v4, s[8:15] dmask:0x1 slc
306 image_atomic_add v9, v5, s[8:15] dmask:0x1 unorm glc slc lwe da
Dmubuf-gfx9.s56 buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 slc
80 buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUAsmGFX7.rst173 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
174 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
175 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
176 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
177 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
178 …x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
179 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
180 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
181 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
182 …_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
[all …]
DAMDGPUAsmGFX8.rst178 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
179 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
180 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
181 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
182 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
183 …x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
184 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
185 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
186 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
187 … dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
[all …]
DAMDGPUAsmGFX9.rst186 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
187 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
188 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
189 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
190 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
191 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
192 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
193 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
194 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
195 …lat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DBUFInstructions.td134 bits<1> slc;
145 offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc, SLC:$slc, TFE:$tfe),
147 offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc, SLC:$slc, TFE:$tfe)
152 SLC:$slc, TFE:$tfe),
155 SLC:$slc, TFE:$tfe)
206 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe",
221 i8:$nfmt, i1:$glc, i1:$slc, i1:$tfe)))]>,
227 i8:$dfmt, i8:$nfmt, i1:$glc, i1:$slc, i1:$tfe)))]>,
252 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe",
267 i1:$slc, i1:$tfe))]>,
[all …]
DFLATInstructions.td88 bits<1> slc;
112 let Inst{17} = slc;
138 (ins GLC:$glc, SLC:$slc)),
140 " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> {
161 (ins GLC:$glc, SLC:$slc)),
162 " $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> {
191 (ins SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc),
192 (ins VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc)),
193 …dst, "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc"> {
207 (ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc),
[all …]
DSIIntrinsics.td33 llvm_i32_ty, // slc(imm)
47 llvm_i32_ty, // slc(imm)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dmubuf_vi.txt12 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x…
21 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0…
33 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x52,0xe0,0x…
42 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52…
54 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x52,0xe0,0x…
63 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52…
75 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x…
84 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04…
96 # VI: buffer_store_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x72,0xe0,0x00,0…
105 # VI: buffer_store_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe…
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dmubuf_vi.txt12 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x…
21 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0…
33 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x52,0xe0,0x…
42 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52…
54 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x52,0xe0,0x…
63 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52…
75 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x…
84 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04…
96 # VI: buffer_store_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x72,0xe0,0x00,0…
105 # VI: buffer_store_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe…
[all …]
/external/adhd/cras/src/server/
Dcras_hfp_iodev.c24 struct hfp_slc_handle *slc; member
105 hfp_set_call_status(hfpio->slc, 1); in configure_dev()
122 hfp_set_call_status(hfpio->slc, 0); in close_dev()
139 hfp_event_speaker_gain(hfpio->slc, volume); in set_hfp_volume()
216 struct hfp_slc_handle *slc, in hfp_iodev_create() argument
233 hfpio->slc = slc; in hfp_iodev_create()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.tbuffer.store.ll5 …[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen offset:32 glc slc
15 …[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 idxen offset:32 glc slc
25 …-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, {{s[0-9]+}} idxen offset:32 glc slc
45 …[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0 offen offset:24 glc slc
55 …[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:11, nfmt:4, 0 offen offset:16 glc slc
65 …format_x {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:4, nfmt:4, 0 offen offset:8 glc slc
Dllvm.SI.load.dword.ll10 ; CHECK: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc
11 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc
12 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc
13 …uffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc
15 …{{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc
Dmemory-legalizer-store.ll209 …ffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
219 …ffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
231 ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
232 ; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}}
242 ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
243 ; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}}
277 ; GFX89: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
287 ; GFX89: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td124 SDTCisVT<11, i32>, // slc(imm)
554 def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
2859 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2861 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2873 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2875 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2919 bits<1> slc;
3030 SCSrc_32:$soffset, offset:$offset, slc:$slc),
3031 name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset$slc", [], 0
3037 slc:$slc),
[all …]
DSIIntrinsics.td35 llvm_i32_ty, // slc(imm)
49 llvm_i32_ty, // slc(imm)
66 llvm_i32_ty, // slc(imm)
81 llvm_i32_ty, // slc(imm)
DSIInstructions.td2158 imm:$glc, imm:$slc)),
2160 (as_i1imm $glc), (as_i1imm $slc), 0)
2166 imm:$glc, imm:$slc)),
2168 (as_i1imm $glc), (as_i1imm $slc), 0)
2174 imm:$glc, imm:$slc)),
2176 (as_i1imm $glc), (as_i1imm $slc), 0)
2182 imm:$glc, imm:$slc)),
2186 (as_i1imm $glc), (as_i1imm $slc), 0)
2202 imm:$glc, imm:$slc),
2204 (as_i1imm $glc), (as_i1imm $slc), 0)
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.load.dword.ll10 ; CHECK: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc
11 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc
12 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc
13 …uffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc
15 …{{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc
/external/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td198 llvm_i1_ty], // slc(imm)
213 llvm_i1_ty], // slc(imm)
226 llvm_i1_ty], // slc(imm)
249 llvm_i1_ty], // slc(imm)
258 llvm_i1_ty], // slc(imm)
270 llvm_i1_ty], // slc(imm)
281 llvm_i1_ty], // slc(imm)
300 llvm_i1_ty], // slc(imm)
/external/python/cpython2/Lib/test/
Dtest_ast.py224 slc = ast.parse("x[::]").body[0].value.slice
225 self.assertIsNone(slc.upper)
226 self.assertIsNone(slc.lower)
227 self.assertIsInstance(slc.step, ast.Name)
228 self.assertEqual(slc.step.id, "None")

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