| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | micromips-delay-slot.ll | 20 ; CHECK-NEXT: sll16
22 ; CHECK-MMR6-NOT: sll16
|
| D | mno-ldc1-sdc1.ll | 264 ; MM: sll16 $[[R0:[0-9]+]], $5, 3
268 ; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $5, 3
277 ; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $5, 3
312 ; MM: sll16 $[[R0:[0-9]+]], $7, 3
316 ; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3
325 ; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $7, 3
|
| D | micromips-shift.ll | 24 ; CHECK: sll16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}}
|
| /external/llvm/test/CodeGen/Mips/ |
| D | micromips-delay-slot.ll | 20 ; CHECK-NEXT: sll16
22 ; CHECK-MMR6-NOT: sll16
|
| D | mno-ldc1-sdc1.ll | 264 ; MM: sll16 $[[R0:[0-9]+]], $5, 3
268 ; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $5, 3
277 ; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $5, 3
312 ; MM: sll16 $[[R0:[0-9]+]], $7, 3
316 ; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3
325 ; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $7, 3
|
| D | micromips-shift.ll | 24 ; CHECK: sll16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}}
|
| /external/llvm/test/MC/Mips/ |
| D | micromips-16-bit-instructions.s | 19 # CHECK-EL: sll16 $3, $16, 5 # encoding: [0x8a,0x25]
74 # CHECK-EB: sll16 $3, $16, 5 # encoding: [0x25,0x8a]
127 sll16 $3, $16, 5
|
| D | micromips-invalid.s | 16 sll16 $1, $16, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
18 sll16 $3, $16, 9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | micromips-16-bit-instructions.s | 19 # CHECK-EL: sll16 $3, $16, 5 # encoding: [0x8a,0x25]
74 # CHECK-EB: sll16 $3, $16, 5 # encoding: [0x25,0x8a]
127 sll16 $3, $16, 5
|
| D | micromips-invalid.s | 16 sll16 $1, $16, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
18 sll16 $3, $16, 9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | lshr.ll | 126 ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1
137 ; MMR6: sll16 $[[T1:[0-9]+]], $4, 1
|
| D | ashr.ll | 132 ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1
149 ; MMR6: sll16 $[[T7:[0-9]+]], $4, 1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | ashr.ll | 369 ; MMR3-NEXT: sll16 $5, $4, 1
389 ; MMR6-NEXT: sll16 $4, $4, 1
805 ; MMR3-NEXT: sll16 $2, $6, 1
826 ; MMR3-NEXT: sll16 $6, $17, 1
901 ; MMR6-NEXT: sll16 $17, $6, 1
914 ; MMR6-NEXT: sll16 $7, $4, 1
|
| D | lshr.ll | 394 ; MMR3-NEXT: sll16 $5, $4, 1
408 ; MMR6-NEXT: sll16 $3, $4, 1
841 ; MMR3-NEXT: sll16 $2, $6, 1
854 ; MMR3-NEXT: sll16 $6, $4, 1
918 ; MMR6-NEXT: sll16 $6, $6, 1
924 ; MMR6-NEXT: sll16 $2, $4, 1
|
| D | shl.ll | 898 ; MMR3-NEXT: sll16 $6, $7, 1
961 ; MMR6-NEXT: sll16 $4, $6, 1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips/ |
| D | valid.s | 30 sll16 $3, $16, 5 # CHECK: sll16 $3, $16, 5 # encoding: [0x25,0x8a] label
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | valid.s | 251 sll16 $3, $6, 8 # CHECK: sll16 $3, $6, 8 # encoding: [0x25,0xe0]
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 30 0x25 0xe0 # CHECK: sll16 $3, $6, 8
228 0x25 0xe0 # CHECK: sll16 $3, $6, 8
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 30 0x25 0xe0 # CHECK: sll16 $3, $6, 8
232 0x25 0xe0 # CHECK: sll16 $3, $6, 8
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid-el.txt | 17 0x8a 0x25 # CHECK: sll16 $3, $16, 5
|
| D | valid.txt | 17 0x25 0x8a # CHECK: sll16 $3, $16, 5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/ |
| D | valid.s | 296 sll16 $3, $6, 8 # CHECK: sll16 $3, $6, 8 # encoding: [0x25,0xe0]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid-el.txt | 17 0x8a 0x25 # CHECK: sll16 $3, $16, 5
|
| D | valid.txt | 17 0x25 0x8a # CHECK: sll16 $3, $16, 5
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 1102 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
1103 MMR6Arch<"sll16">;
|