| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | smul.ll | 77 ; CHECK: smlawb r0, r0, r1, r2
78 ; CHECK-THUMBV6-NOT: smlawb
93 ; CHECK: smlawb r0, r0, r1, r2
94 ; CHECK-THUMBV6-NOT: smlawb
283 ; CHECK: smlawb r0, r0, r2, r1
284 ; CHECK-THUMBV6-NOT: smlawb
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| D | acle-intrinsics-v5.ll | 56 ; CHECK: smlawb r2, r0, r1, r2
62 %acc5 = call i32 @llvm.arm.smlawb(i32 %a, i32 %b, i32 %acc4)
107 declare i32 @llvm.arm.smlawb(i32, i32, i32) nounwind
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| /external/llvm/test/CodeGen/ARM/ |
| D | smul.ll | 70 ; CHECK: smlawb
84 ; CHECK: smlawb
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| /external/arm-neon-tests/ |
| D | ref_dsp.c | 409 sres = smlawb(svar1, svar2, sacc); in exec_dsp()
416 sres = smlawb(svar1, svar2, sacc); in exec_dsp()
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| D | ref-rvct-all.txt | 8038 smlawb(0x12345678, 0x12345678, 0x1020304) = 0x7282098
8040 smlawb(0xf123f456, 0xf123f456, 0x1020304) = 0x1af55a4
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 669 0x83,0x8a,0x22,0xe1 = smlawb r2, r3, r10, r8
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| D | basic-thumb2-instructions.s.cs | 744 0x33,0xfb,0x0a,0x82 = smlawb r2, r3, r10, r8
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1676 smlawb r2, r3, r10, r8
1681 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x83,0x8a,0x22,0xe1]
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| D | basic-thumb2-instructions.s | 1920 smlawb r2, r3, r10, r8
1926 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x33,0xfb,0x0a,0x82]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3135 void smlawb(
3137 void smlawb(Register rd, Register rn, Register rm, Register ra) { in smlawb() function
3138 smlawb(al, rd, rn, rm, ra); in smlawb()
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| D | disasm-aarch32.h | 1127 void smlawb(
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| D | disasm-aarch32.cc | 2658 void Disassembler::smlawb( in smlawb() function in vixl::aarch32::Disassembler
22220 smlawb(CurrentCond(), in DecodeT32()
56485 smlawb(condition, in DecodeA32()
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| D | assembler-aarch32.cc | 10178 void Assembler::smlawb( in smlawb() function in vixl::aarch32::Assembler
10201 Delegate(kSmlawb, &Assembler::smlawb, cond, rd, rn, rm, ra); in smlawb()
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2449 smlawb r2, r3, r10, r8
2454 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x83,0x8a,0x22,0xe1]
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| D | basic-thumb2-instructions.s | 2355 smlawb r2, r3, r10, r8
2361 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x33,0xfb,0x0a,0x82]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2451 smlawb r2, r3, r10, r8
2456 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x83,0x8a,0x22,0xe1]
|
| D | basic-thumb2-instructions.s | 2403 smlawb r2, r3, r10, r8
2409 @ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x33,0xfb,0x0a,0x82]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1505 # CHECK: smlawb r2, r3, r10, r8
|
| D | thumb2.txt | 1699 # CHECK: smlawb r2, r3, r10, r8
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1657 # CHECK: smlawb r2, r3, r10, r8
|
| D | thumb2.txt | 1838 # CHECK: smlawb r2, r3, r10, r8
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1657 # CHECK: smlawb r2, r3, r10, r8
|
| D | thumb2.txt | 1838 # CHECK: smlawb r2, r3, r10, r8
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2782 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 8701 …{ 1075 /* smlawb */, ARM::t2SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_…
8702 …{ 1075 /* smlawb */, ARM::SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_Is…
|