| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 368 define i32 @smlsd(i32 %a, i32 %b, i32 %c) nounwind {
369 ; CHECK-LABEL: smlsd
370 ; CHECK: smlsd r0, r0, r1, r2
371 %tmp = call i32 @llvm.arm.smlsd(i32 %a, i32 %b, i32 %c)
474 declare i32 @llvm.arm.smlsd(i32, i32, i32) nounwind
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 673 0x53,0x85,0x02,0xe7 = smlsd r2, r3, r5, r8
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| D | basic-thumb2-instructions.s.cs | 749 0x43,0xfb,0x05,0x82 = smlsd r2, r3, r5, r8
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1690 smlsd r2, r3, r5, r8
1695 @ CHECK: smlsd r2, r3, r5, r8 @ encoding: [0x53,0x85,0x02,0xe7]
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| D | basic-thumb2-instructions.s | 1936 smlsd r2, r3, r5, r8
1942 @ CHECK: smlsd r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x05,0x82]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3147 void smlsd(
3149 void smlsd(Register rd, Register rn, Register rm, Register ra) { in smlsd() function
3150 smlsd(al, rd, rn, rm, ra); in smlsd()
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| D | disasm-aarch32.h | 1133 void smlsd(
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| D | disasm-aarch32.cc | 2672 void Disassembler::smlsd( in smlsd() function in vixl::aarch32::Disassembler
21973 smlsd(CurrentCond(), in DecodeT32()
63855 smlsd(condition, in DecodeA32()
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| D | assembler-aarch32.cc | 10230 void Assembler::smlsd( in smlsd() function in vixl::aarch32::Assembler
10252 Delegate(kSmlsd, &Assembler::smlsd, cond, rd, rn, rm, ra); in smlsd()
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| D | macro-assembler-aarch32.h | 3786 smlsd(cond, rd, rn, rm, ra); in Smlsd()
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2463 smlsd r2, r3, r5, r8
2468 @ CHECK: smlsd r2, r3, r5, r8 @ encoding: [0x53,0x85,0x02,0xe7]
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| D | basic-thumb2-instructions.s | 2371 smlsd r2, r3, r5, r8
2377 @ CHECK: smlsd r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x05,0x82]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2465 smlsd r2, r3, r5, r8
2470 @ CHECK: smlsd r2, r3, r5, r8 @ encoding: [0x53,0x85,0x02,0xe7]
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| D | basic-thumb2-instructions.s | 2419 smlsd r2, r3, r5, r8
2425 @ CHECK: smlsd r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x05,0x82]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1519 # CHECK: smlsd r2, r3, r5, r8
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| D | thumb2.txt | 1715 # CHECK: smlsd r2, r3, r5, r8
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1671 # CHECK: smlsd r2, r3, r5, r8
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| D | thumb2.txt | 1854 # CHECK: smlsd r2, r3, r5, r8
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1671 # CHECK: smlsd r2, r3, r5, r8
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| D | thumb2.txt | 1854 # CHECK: smlsd r2, r3, r5, r8
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2657 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2857 def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd", int_arm_smlsd>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2885 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7756 "lawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smmla\006smml"
8705 …{ 1089 /* smlsd */, ARM::t2SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_Is…
8706 …{ 1089 /* smlsd */, ARM::SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsAR…
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| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1181 arm_smlsd, // llvm.arm.smlsd
|