| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 375 define i32 @smlsdx(i32 %a, i32 %b, i32 %c) nounwind {
376 ; CHECK-LABEL: smlsdx
377 ; CHECK: smlsdx r0, r0, r1, r2
378 %tmp = call i32 @llvm.arm.smlsdx(i32 %a, i32 %b, i32 %c)
475 declare i32 @llvm.arm.smlsdx(i32, i32, i32) nounwind
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 674 0x73,0x85,0x02,0xe7 = smlsdx r2, r3, r5, r8
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| D | basic-thumb2-instructions.s.cs | 750 0x43,0xfb,0x15,0x82 = smlsdx r2, r3, r5, r8
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1691 smlsdx r2, r3, r5, r8
1696 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x73,0x85,0x02,0xe7]
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| D | basic-thumb2-instructions.s | 1937 smlsdx r2, r3, r5, r8
1943 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x15,0x82]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3153 void smlsdx(
3155 void smlsdx(Register rd, Register rn, Register rm, Register ra) { in smlsdx() function
3156 smlsdx(al, rd, rn, rm, ra); in smlsdx()
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| D | disasm-aarch32.h | 1136 void smlsdx(
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| D | disasm-aarch32.cc | 2679 void Disassembler::smlsdx( in smlsdx() function in vixl::aarch32::Disassembler
22008 smlsdx(CurrentCond(), in DecodeT32()
63894 smlsdx(condition, in DecodeA32()
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| D | assembler-aarch32.cc | 10255 void Assembler::smlsdx( in smlsdx() function in vixl::aarch32::Assembler
10277 Delegate(kSmlsdx, &Assembler::smlsdx, cond, rd, rn, rm, ra); in smlsdx()
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| D | macro-assembler-aarch32.h | 3802 smlsdx(cond, rd, rn, rm, ra); in Smlsdx()
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2464 smlsdx r2, r3, r5, r8
2469 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x73,0x85,0x02,0xe7]
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| D | basic-thumb2-instructions.s | 2372 smlsdx r2, r3, r5, r8
2378 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x15,0x82]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2466 smlsdx r2, r3, r5, r8
2471 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x73,0x85,0x02,0xe7]
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| D | basic-thumb2-instructions.s | 2420 smlsdx r2, r3, r5, r8
2426 @ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x15,0x82]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1520 # CHECK: smlsdx r2, r3, r5, r8
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| D | thumb2.txt | 1716 # CHECK: smlsdx r2, r3, r5, r8
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1672 # CHECK: smlsdx r2, r3, r5, r8
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| D | thumb2.txt | 1855 # CHECK: smlsdx r2, r3, r5, r8
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1672 # CHECK: smlsdx r2, r3, r5, r8
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| D | thumb2.txt | 1855 # CHECK: smlsdx r2, r3, r5, r8
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2661 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2858 def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx", int_arm_smlsdx>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2889 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7756 "lawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smmla\006smml"
8707 …{ 1095 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_…
8708 …{ 1095 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_Is…
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| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1182 arm_smlsdx, // llvm.arm.smlsdx
|