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/external/libhevc/common/arm64/
Dihevc_itrans_recon_8x8.s187 smull v20.4s, v2.4h, v0.h[0] //// y0 * cos4(part of c0 and c1)
189 smull v18.4s, v3.4h, v1.h[2] //// y2 * sin2 (q3 is freed by this time)(part of d1)
192 smull v24.4s, v6.4h, v0.h[1] //// y1 * cos1(part of b0)
194 smull v26.4s, v6.4h, v0.h[3] //// y1 * cos3(part of b1)
196 smull v28.4s, v6.4h, v1.h[1] //// y1 * sin3(part of b2)
198 smull v30.4s, v6.4h, v1.h[3] //// y1 * sin1(part of b3)
208 smull v22.4s, v10.4h, v0.h[0] //// y4 * cos4(part of c0 and c1)
210 smull v6.4s, v3.4h, v0.h[2] //// y2 * cos2(part of d0)
304 smull v24.4s, v6.4h, v0.h[1] //// y1 * cos1(part of b0)
305 smull v26.4s, v6.4h, v0.h[3] //// y1 * cos3(part of b1)
[all …]
Dihevc_inter_pred_chroma_vert_w16inp_w16out.s144 smull v0.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
147 smull v7.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
191 smull v30.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
199 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
212 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
222 smull v24.4s, v3.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
238 smull v30.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
248 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
261 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
273 smull v24.4s, v3.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
[all …]
Dihevc_inter_pred_chroma_vert_w16inp.s144 smull v0.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
147 smull v7.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
192 smull v30.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
200 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
213 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
224 smull v24.4s, v3.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
241 smull v30.4s, v0.4h, v16.4h //vmull_s16(src_tmp1, coeff_0)
252 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
266 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
279 smull v24.4s, v3.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
[all …]
Dihevc_weighted_pred_bi.s222 smull v4.4s, v0.4h, v7.h[0] //vmull_n_s16(pi2_src1_val1, (int16_t) wgt0)
224 smull v5.4s, v1.4h, v7.h[1] //vmull_n_s16(pi2_src2_val1, (int16_t) wgt1)
229 … smull v6.4s, v2.4h, v7.h[0] //vmull_n_s16(pi2_src1_val2, (int16_t) wgt0) ii iteration
233 … smull v19.4s, v0.4h, v7.h[0] //vmull_n_s16(pi2_src1_val1, (int16_t) wgt0) iii iteration
236 … smull v17.4s, v3.4h, v7.h[1] //vmull_n_s16(pi2_src2_val2, (int16_t) wgt1) ii iteration
243 … smull v16.4s, v1.4h, v7.h[1] //vmull_n_s16(pi2_src2_val1, (int16_t) wgt1) iii iteration
251 … smull v18.4s, v2.4h, v7.h[0] //vmull_n_s16(pi2_src1_val2, (int16_t) wgt0) iv iteration
257 … smull v20.4s, v3.4h, v7.h[1] //vmull_n_s16(pi2_src2_val2, (int16_t) wgt1) iv iteration
Dihevc_itrans_recon_4x4_ttype1.s140 smull v6.4s, v1.4h, v4.h[2] //74 * pi2_src[1]
145 smull v5.4s, v1.4h, v4.h[2] //74 * pi2_src[1]
150 smull v7.4s, v0.4h, v4.h[2] // 74 * pi2_src[0]
154 smull v20.4s, v2.4h, v4.h[1] // 55 * pi2_src[2]
183 smull v6.4s, v22.4h, v4.h[2] //74 * pi2_src[1]
188 smull v5.4s, v22.4h, v4.h[2] //74 * pi2_src[1]
193 smull v7.4s, v21.4h, v4.h[2] // 74 * pi2_src[0]
198 smull v20.4s, v16.4h, v4.h[1] // 55 * pi2_src[2]
Dihevc_itrans_recon_16x16.s255 smull v24.4s, v6.4h, v0.h[1] //// y1 * cos1(part of b0)
256 smull v26.4s, v6.4h, v0.h[3] //// y1 * cos3(part of b1)
257 smull v28.4s, v6.4h, v1.h[1] //// y1 * sin3(part of b2)
258 smull v30.4s, v6.4h, v1.h[3] //// y1 * sin1(part of b3)
270 smull v12.4s, v10.4h, v0.h[0]
272 smull v14.4s, v10.4h, v0.h[0]
274 smull v16.4s, v10.4h, v0.h[0]
276 smull v18.4s, v10.4h, v0.h[0]
433 smull v24.4s, v6.4h, v2.h[1] //// y1 * cos1(part of b0)
434 smull v26.4s, v6.4h, v2.h[3] //// y1 * cos3(part of b1)
[all …]
Dihevc_inter_pred_filters_luma_vert_w16inp.s155 smull v19.4s, v1.4h, v23.4h //mul_res1 = vmull_u8(src_tmp2, coeffabs_1)//
171 smull v20.4s, v2.4h, v23.4h //mul_res2 = vmull_u8(src_tmp3, coeffabs_1)//
188 smull v21.4s, v3.4h, v23.4h
202 smull v30.4s, v4.4h, v23.4h
229 smull v19.4s, v1.4h, v23.4h //mul_res1 = vmull_u8(src_tmp2, coeffabs_1)//
246 smull v20.4s, v2.4h, v23.4h //mul_res2 = vmull_u8(src_tmp3, coeffabs_1)//
262 smull v21.4s, v3.4h, v23.4h
289 smull v30.4s, v4.4h, v23.4h
316 smull v19.4s, v1.4h, v23.4h //mul_res1 = vmull_u8(src_tmp2, coeffabs_1)//
330 smull v20.4s, v2.4h, v23.4h //mul_res2 = vmull_u8(src_tmp3, coeffabs_1)//
[all …]
Dihevc_inter_pred_luma_vert_w16inp_w16out.s166 smull v19.4s,v1.4h,v23.4h //mul_res1 = smull_u8(src_tmp2, coeffabs_1)//
182 smull v20.4s,v2.4h,v23.4h //mul_res2 = smull_u8(src_tmp3, coeffabs_1)//
199 smull v21.4s,v3.4h,v23.4h
214 smull v31.4s,v4.4h,v23.4h
243 smull v19.4s,v1.4h,v23.4h //mul_res1 = smull_u8(src_tmp2, coeffabs_1)//
261 smull v20.4s,v2.4h,v23.4h //mul_res2 = smull_u8(src_tmp3, coeffabs_1)//
278 smull v21.4s,v3.4h,v23.4h
306 smull v31.4s,v4.4h,v23.4h
334 smull v19.4s,v1.4h,v23.4h //mul_res1 = smull_u8(src_tmp2, coeffabs_1)//
349 smull v20.4s,v2.4h,v23.4h //mul_res2 = smull_u8(src_tmp3, coeffabs_1)//
[all …]
Dihevc_weighted_pred_uni.s175 smull v4.4s, v1.4h, v0.h[0] //vmull_n_s16(pi2_src_val1, (int16_t) wgt0)
180 smull v6.4s, v2.4h, v0.h[0] //vmull_n_s16(pi2_src_val2, (int16_t) wgt0) ii iteration
187 … smull v7.4s, v3.4h, v0.h[0] //vmull_n_s16(pi2_src_val1, (int16_t) wgt0) iii iteration
196 smull v16.4s, v5.4h, v0.h[0] //vmull_n_s16(pi2_src_val2, (int16_t) wgt0) iv iteration
Dihevc_itrans_recon_32x32.s213 smull v24.4s, v8.4h, v0.h[1] //// y1 * cos1(part of b0)
214 smull v26.4s, v8.4h, v0.h[3] //// y1 * cos3(part of b1)
215 smull v28.4s, v8.4h, v1.h[1] //// y1 * sin3(part of b2)
216 smull v30.4s, v8.4h, v1.h[3] //// y1 * sin1(part of b3)
227 smull v20.4s, v10.4h, v0.h[0]
231 smull v22.4s, v10.4h, v0.h[0]
234 smull v16.4s, v10.4h, v0.h[0]
237 smull v18.4s, v10.4h, v0.h[0]
574 smull v24.4s, v8.4h, v2.h[1] //// y1 * cos1(part of b0)
575 smull v26.4s, v8.4h, v2.h[3] //// y1 * cos3(part of b1)
[all …]
Dihevc_itrans_recon_4x4.s143 smull v6.4s, v1.4h, v4.h[1] //83 * pi2_src[1]
145 smull v5.4s, v1.4h, v4.h[3] //36 * pi2_src[1]
176 smull v6.4s, v1.4h, v4.h[1] //83 * pi2_src[1]
179 smull v5.4s, v1.4h, v4.h[3] //36 * pi2_src[1]
/external/libmpeg2/common/armv8/
Dimpeg2_idct.s387 smull v20.4s, v2.4h, v0.h[0] //// y0 * cos4(part of c0 and c1)
389 smull v18.4s, v3.4h, v1.h[2] //// y2 * sin2 (q3 is freed by this time)(part of d1)
392 smull v24.4s, v6.4h, v0.h[1] //// y1 * cos1(part of b0)
394 smull v26.4s, v6.4h, v0.h[3] //// y1 * cos3(part of b1)
396 smull v28.4s, v6.4h, v1.h[1] //// y1 * sin3(part of b2)
398 smull v30.4s, v6.4h, v1.h[3] //// y1 * sin1(part of b3)
408 smull v22.4s, v10.4h, v0.h[0] //// y4 * cos4(part of c0 and c1)
410 smull v6.4s, v3.4h, v0.h[2] //// y2 * cos2(part of d0)
505 smull v24.4s, v6.4h, v0.h[1] //// y1 * cos1(part of b0)
506 smull v26.4s, v6.4h, v0.h[3] //// y1 * cos3(part of b1)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/AArch64/
D2012-04-23-Neon-Intrinsics.ll7 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) n…
15 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16…
24 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4…
32 …%b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>…
48 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4…
52 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 …
58 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4…
66 declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dmulhi.ll10 ; V4: smull
13 ; M3: smull
45 ; V4: smull
49 ; M3: smull
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dmulhi.ll10 ; V4: smull
13 ; M3: smull
45 ; V4: smull
49 ; M3: smull
/external/llvm/test/CodeGen/ARM/
Dmulhi.ll10 ; V4: smull
13 ; M3: smull
45 ; V4: smull
49 ; M3: smull
/external/llvm/test/Transforms/InstCombine/
D2012-04-23-Neon-Intrinsics.ll71 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) n…
79 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16…
88 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4…
96 …%b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>…
112 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4…
116 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 …
122 …%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4…
130 declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s147 smull v0.4s, v16.4h, v20.4h // q0 = p[i] = (x[i] * trns_coeff[i]) where i = 0..3
148 smull v2.4s, v17.4h, v21.4h // q1 = p[i] = (x[i] * trns_coeff[i]) where i = 4..7
149 smull v4.4s, v18.4h, v22.4h // q2 = p[i] = (x[i] * trns_coeff[i]) where i = 8..11
150 smull v6.4s, v19.4h, v23.4h // q3 = p[i] = (x[i] * trns_coeff[i]) where i = 12..15
340 smull v0.4s, v16.4h, v20.4h // q0 = p[i] = (x[i] * trns_coeff[i]) where i = 0..3
341 smull v2.4s, v17.4h, v21.4h // q1 = p[i] = (x[i] * trns_coeff[i]) where i = 4..7
342 smull v4.4s, v18.4h, v22.4h // q2 = p[i] = (x[i] * trns_coeff[i]) where i = 8..11
343 smull v6.4s, v19.4h, v23.4h // q3 = p[i] = (x[i] * trns_coeff[i]) where i = 12..15
560 smull v16.4s, v0.4h, v8.4h
562 smull v18.4s, v1.4h, v9.4h
[all …]
Dih264_resi_trans_quant_av8.s171 smull v0.4s, v0.4h, v28.4h //multiply and add row 1
172 smull v1.4s, v1.4h, v29.4h //multiply and add row 2
173 smull v2.4s, v2.4h, v30.4h //multiply and add row 3
174 smull v3.4s, v3.4h, v31.4h //multiply and add row 4
373 smull v0.4s, v0.4h, v28.4h //multiply and add row 1
374 smull v1.4s, v1.4h, v29.4h //multiply and add row 2
375 smull v2.4s, v2.4h, v30.4h //multiply and add row 3
376 smull v3.4s, v3.4h, v31.4h //multiply and add row 4
/external/libjpeg-turbo/simd/arm64/
Djsimd_neon.S493 … smull v18.4s, v18.4h, XFIX_P_0_541 /* z1l z1 = MULTIPLY(z2 + z3, FIX_0_541196100); */
533 smull v10.4s, v9.4h, XFIX_P_0_298 /* tmp0 = MULTIPLY(tmp0, FIX_0_298631336) */
534 smull v12.4s, v7.4h, XFIX_P_2_053 /* tmp1 = MULTIPLY(tmp1, FIX_2_053119869) */
535 smull v14.4s, v5.4h, XFIX_P_3_072 /* tmp2 = MULTIPLY(tmp2, FIX_3_072711026) */
536 smull v16.4s, v3.4h, XFIX_P_1_501 /* tmp3 = MULTIPLY(tmp3, FIX_1_501321110) */
537 smull v26.4s, v26.4h, XFIX_P_1_175 /* z5l z5 = MULTIPLY(z3 + z4, FIX_1_175875602) */
538 smull v22.4s, v22.4h, XFIX_N_1_961 /* z3 = MULTIPLY(z3, -FIX_1_961570560) */
539 smull v24.4s, v24.4h, XFIX_N_0_390 /* z4 = MULTIPLY(z4, -FIX_0_390180644) */
540 smull v18.4s, v18.4h, XFIX_N_0_899 /* z1 = MULTIPLY(z1, -FIX_0_899976223) */
541 smull v20.4s, v20.4h, XFIX_N_2_562 /* z2 = MULTIPLY(z2, -FIX_2_562915447) */
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-mul-div-cte.ll7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
Daarch64-smull.ll5 ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
16 ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
27 ; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
228 ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
246 ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
254 ; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
295 ; If one operand has a zero-extend and the other a sign-extend, smull
Darm64-neon-2velem-high.ll15 …%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %ve…
26 …%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i1…
39 …%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vec…
50 …%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32…
165 …%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %v…
177 …%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i…
191 …%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %v…
203 …%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i…
327 …%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %v…
339 …%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i…
[all …]
/external/llvm/test/CodeGen/AArch64/
Daarch64-smull.ll5 ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
16 ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
27 ; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
228 ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
246 ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
254 ; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
295 ; If one operand has a zero-extend and the other a sign-extend, smull
Darm64-neon-2velem-high.ll15 …%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %ve…
26 …%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i1…
39 …%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vec…
50 …%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32…
165 …%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %v…
177 …%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i…
191 …%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %v…
203 …%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i…
327 …%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %v…
339 …%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i…
[all …]

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