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Searched refs:smultb (Results 1 – 25 of 28) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dacle-intrinsics-v5.ll22 define i32 @smultb(i32 %a, i32 %b) {
23 ; CHECK-LABEL: smultb
24 ; CHECK: smultb r0, r0, r1
25 %tmp = call i32 @llvm.arm.smultb(i32 %a, i32 %b)
99 declare i32 @llvm.arm.smultb(i32 %a, i32 %b) nounwind readnone
Dsmul.ll10 ; CHECK: {{smulbt r0, r0, r1|smultb r0, r1, r0}}
11 ; CHECK-THUMBV6-NOT: {{smulbt|smultb}}
161 ; CHECK: {{smultb r0, r0, r1|smulbt r0, r1, r0}}
162 ; CHECK-THUMBV6-NOT: {{smultb|smulbt}}
172 ; CHECK: {{smultb r0, r0, r1|smulbt r0, r1, r0}}
173 ; CHECK-THUMBV6-NOT: {{smultb|smulbt}}
184 ; CHECK: {{smulbt r0, r0, r1|smultb r0, r1, r0}}
185 ; CHECK-THUMBV6-NOT: {{smulbt|smultb}}
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-smla.ll8 ; NO_MULOPS: smultb r1, r2, r1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dthumb2-smla.ll8 ; NO_MULOPS: smultb r1, r2, r1
/external/arm-neon-tests/
Dref_dsp.c272 sres = smultb(svar1, svar2); in exec_dsp()
283 sres = smultb(svar1, svar2); in exec_dsp()
Dref-rvct-all.txt8008 smultb(0x12345678, 0x12345678) = 0x6260060
8012 smultb(0xf123f456, 0xf123f456) = 0xad5dc2
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-t32.cc72 M(smultb) \
Dtest-assembler-cond-rd-rn-rm-a32.cc73 M(smultb) \
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs699 0xa2,0x02,0x64,0xe1 = smultb r4, r2, r2
Dbasic-thumb2-instructions.s.cs781 0x12,0xfb,0x22,0xf4 = smultb r4, r2, r2
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s1776 smultb r4, r2, r2
1785 @ CHECK: smultb r4, r2, r2 @ encoding: [0xa2,0x02,0x64,0xe1]
Dbasic-thumb2-instructions.s2034 smultb r4, r2, r2
2044 @ CHECK: smultb r4, r2, r2 @ encoding: [0x12,0xfb,0x22,0xf4]
/external/vixl/src/aarch32/
Dassembler-aarch32.h3225 void smultb(Condition cond, Register rd, Register rn, Register rm);
3226 void smultb(Register rd, Register rn, Register rm) { smultb(al, rd, rn, rm); } in smultb() function
Ddisasm-aarch32.h1175 void smultb(Condition cond, Register rd, Register rn, Register rm);
Ddisasm-aarch32.cc2820 void Disassembler::smultb(Condition cond, in smultb() function in vixl::aarch32::Disassembler
22134 smultb(CurrentCond(), in DecodeT32()
56549 smultb(condition, in DecodeA32()
Dassembler-aarch32.cc10619 void Assembler::smultb(Condition cond, Register rd, Register rn, Register rm) { in smultb() function in vixl::aarch32::Assembler
10639 Delegate(kSmultb, &Assembler::smultb, cond, rd, rn, rm); in smultb()
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2549 smultb r4, r2, r2
2558 @ CHECK: smultb r4, r2, r2 @ encoding: [0xa2,0x02,0x64,0xe1]
Dbasic-thumb2-instructions.s2469 smultb r4, r2, r2
2479 @ CHECK: smultb r4, r2, r2 @ encoding: [0x12,0xfb,0x22,0xf4]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2551 smultb r4, r2, r2
2560 @ CHECK: smultb r4, r2, r2 @ encoding: [0xa2,0x02,0x64,0xe1]
Dbasic-thumb2-instructions.s2517 smultb r4, r2, r2
2527 @ CHECK: smultb r4, r2, r2 @ encoding: [0x12,0xfb,0x22,0xf4]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1605 # CHECK: smultb r4, r2, r2
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1757 # CHECK: smultb r4, r2, r2
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1757 # CHECK: smultb r4, r2, r2
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td2726 def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7758 "smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005smusd\006smu"
8736 …{ 1189 /* smultb */, ARM::t2SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2…
8737 …{ 1189 /* smultb */, ARM::SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feat…

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