Searched refs:spilled (Results 1 – 25 of 251) sorted by relevance
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948 CSRegSet spilled = BI->second; in verifySpillRestorePlacement() local951 if (spilled.empty()) in verifySpillRestorePlacement()955 << stringifyCSRegSet(spilled) in verifySpillRestorePlacement()959 if (CSRRestore[MBB].intersects(spilled)) { in verifySpillRestorePlacement()960 restored |= (CSRRestore[MBB] & spilled); in verifySpillRestorePlacement()973 if (CSRSave[SBB].intersects(spilled) && in verifySpillRestorePlacement()974 !restored.contains(CSRSave[SBB] & spilled)) in verifySpillRestorePlacement()978 if (CSRRestore[SBB].intersects(spilled)) in verifySpillRestorePlacement()979 restored |= (CSRRestore[SBB] & spilled); in verifySpillRestorePlacement()984 if (restored != spilled) { in verifySpillRestorePlacement()[all …]
146 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);491 void RegAllocPBQP::addStackInterval(const LiveInterval *spilled, in addStackInterval() argument493 int stackSlot = vrm->getStackSlot(spilled->reg); in addStackInterval()499 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg); in addStackInterval()510 LiveInterval &rhsInterval = lis->getInterval(spilled->reg); in addStackInterval()
14 ; C is spilled because of the scheduling of the instructions,15 ; but a smarter regalloc wouldn't have spilled it.
3 ; Check proper alignment of spilled vector20 ; Check that proper alignment of spilled vector does not affect vargs
9 ; CHECK-NOT: spilled
13 ; VAL should be spilled before csr_noregs, i.e., before we clobber all the registers
5 ;; Check that they are spilled early enough that not copies are needed for the
16 ; The vector must be spilled:41 ; The vector must not be spilled:
6 ; RUN: llc < %s -march=x86 -stats |& not grep spilled
4 ; of spilled/filled.
3 ; Test that scratch registers are spilled around patchpoints
36 ; %8 is going to be spilled.43 ; %9 us going to be spilled.
9 ; Load the stack guard for the second time, just in case the previous value gets spilled.
141 new (curr) LiveRangeBound(i, i->spilled()); in Initialize()443 DCHECK(!HasRegisterAssigned() && !spilled()); in set_assigned_register()449 DCHECK(HasRegisterAssigned() && !spilled()); in UnsetAssignedRegister()455 DCHECK(!spilled()); in Spill()549 DCHECK(!spilled()); in GetAssignedOperand()553 DCHECK(spilled()); in GetAssignedOperand()1050 temp->set_spilled(first->spilled()); in Merge()1051 if (!temp->spilled()) in Merge()2727 DCHECK(!range->spilled()); in Spill()2774 if (!to_add->spilled()) { in AllocateRegisters()[all …]
328 ; Loc 0: Register (some register that will be spilled to the stack)353 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled373 ; Loc 3: Arg2 spilled to FP -96378 ; Loc 4: Arg3 spilled to FP - 88